Single Bit and 4-Bit Comparator: Truth Table, Boolean Equations, VHDL Code, and Waveforms, Slides of Computer Science

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Single bit comparator

Single bit comparator

A(1)

A(0)

gr: a(1) >a(0) sm: a(1) <a(0) eq: a(1)=a(0)

Truth table

A(1) A(0) Gr Sm Eq

VHDL Code

• entity singlebitcomparator is
• Port ( a : in std_logic_vector(1 downto 0); en: in std_logic;
• gt : out std_logic;
• sm : out std_logic;
• eq : out std_logic);
• end singlebitcomparator;
• architecture Behavioral of singlebitcomparator is
• begin
• process (en,a)
• begin
• if (a(1)>a(0)) then
• gt <= '1'; sm <= '0'; eq <= '0';
• elsif (a(1) < a(0)) then
• gt <= '0'; sm <= '1'; eq <= '0';
• else
• gt <= '0'; sm <= '0'; eq <= '1';
• end if;
• end process;
• end Behavioral;

Waveform of single bit

comparator

Boolean equation for 4-bit

comparator

• Let A=a3a2a1a

• Let B=b3b2b1b

• Intermediate signal : i3,i2,i1 and i

• AeqB= i3i2i1i

• AgtB = a3(b3bar)+i3a2(b2bar)+i3i2a1(b1bar)+i3i2i1a0(b0bar)

• AltB = Not(AeqB+AgtB)

VHDL code of 4-bit comp

• entity comp4bit is
• Port ( x : in std_logic_vector(3 downto 0);
• y : in std_logic_vector(3 downto 0);
• en: in std_logic;
• greater : out std_logic;
• smaller : out std_logic;
• equal : out std_logic);
• end comp4bit;
• architecture Behavioral of comp4bit is
• component singlebitcomparator is
• Port ( a : in std_logic_vector(1 downto 0);
• en: in std_logic;
• gt : out std_logic;
• sm : out std_logic;
• eq : out std_logic);
• end component singlebitcomparator;
• signal temp : std_logic_vector(10 downto 0);

Waveform of 4-bit comparator