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ECE 367 - Microprocessor-Based Design Final Examination (30 problems) 2 hours, closed book and notes, calculators not permitted.
IMPORTANT: Please be aware that academic dishonesty will result in grade E for the course, and possibly dismissal from the University. Looking at another exam paper, showing someone your exam paper, violating the closed book/notes rule, or otherwise communicating exam problem information to/from another student during the exam is considered to be academically dishonest. Should you have any questions about this policy or about any of the exam questions, please step up to the front and ask the instructor for clarification.
- What value (in base 10) is represented by the byte $F0 when the code being used is
a) unsigned binary:
b) signed (2's complement) binary:
- What are the values of C and V flags after these 68HC11 assembly language instruction are executed?
LDAA #$ SUBA #$FF
- What is the address of the first data byte (storing $FA) in "Table" below?
ORG $E Start: JSR Configure BRA * Table: FCB $FA,$FB,$FC,$FD,$FE
- What are the contents of register IY after instruction " LDY #Table " executes in the code below?
ORG $F Table: FCB $02,$03,$ LDY #Table
- What are the contents of register IY after instruction " LDY Table " executes in the code below?
ORG $F Table: FCB $02,$03,$ LDY Table
C = , V =
$ __ __ __ __
$ __ __ __ __
$ __ __ __ __
- Write an interrupt service routine named " Service_TOF " that increments the word of data at memory location Count every time TCNT overflows, and then clears the flag TOF so that this interrupt is re-enabled:
- What prescaling factor and ∆TCNT value would you use when writing interrupt-driven code to execute exactly every 0.1 sec? (E = 2MHz)
Prescaling factor N = ___ , ∆TCNT = ____________
- What are two advantages of driving seven-segment displays in a time- multiplexed manner (as compared to not multiplexing)?
a)
b)
- What are two advantages of not time-multiplexing seven-segment displays?
a)
b)
- Draw a circuit interfacing a 3-column by 4-row matrix keypad to the 68HC11, so that an interrupt occurs every time any key is pressed (it should be possible for software to later determine exactly which key had been pressed):
- Write code to configure an interrupt to occur when TOC2 = TCNT:
- What page of memory is accessed using the direct addressing mode?
- What page of memory is the register block mapped to by default?
Page: ( ) (^10)
Page: ( ) (^10)
- Design a circuit that creates two 16-bit output ports by interfacing PORTB of the M68HC11 microcontroller to four 74HC373 octal latches. Assume that this μC is operating in single-chip mode, and that the lowest 4 bits of PORTD (configured as outputs) are also available for this interfacing task.
Useful information:
- Microcontroller output line STRB is normally high, but is pulsed low for two clock cycles when PORTB is written to
- You may include digital logic gates as required
M68HC
PB7PB PB5PB PB PB2PB PB
PD3PD PD0PD
STRB
8Q 7Q6Q 5Q 4Q3Q 2Q1Q
8D 7D6D 5D 4D3D 2D1D
LE
OE
74HC
8Q7Q 6Q5Q 4Q3Q 2Q 1Q
8D7D 6D5D 4D3D 2D 1D
LE
OE
74HC
16
8
16-bit Output Port #
8Q 7Q6Q 5Q 3Q4Q 2Q1Q
8D 7D6D 5D 3D4D 2D1D
LE
OE
74HC
8Q7Q 6Q5Q 3Q4Q 2Q 1Q
8D7D 6D5D 3D4D 2D 1D
LE
OE
74HC
16
8
16-bit Output Port #
(MSB)
(LSB)
(MSB)
(LSB)
- Design a circuit that creates two memory-mapped output ports by interfacing the address and data busses of the M68HC12 microcontroller (they are not multiplexed) to two 74HC373 octal latches. The addresses of these two output ports should be $2000 and $2001. As these are the only external memory bytes, partial address decoding may be used.
Useful information:
- Microcontroller output line E = 1 and R/ W=0 when a memory write operation occurs
- You may include multi-input digital logic gates as required
M68HC
8Q7Q 6Q5Q 4Q 2Q3Q 1Q
7D8D 6D5D 4D 3D2D 1D
LE
OC
74HC
8
Output Port $
7Q8Q 6Q5Q 4Q 3Q2Q 1Q
8D7D 6D5D 4D 3D2D 1D
LE
OC
74HC
8
Output Port $
E
R / W
a a14a a12a a a9a a7a a a4a a a1a
d7d d5d d3d d d
- Assume that the 68HC11 microcontroller communicates asynchronously with a serial device whose bit rate is exactly 4800 baud. The data exchange takes place using 9 data bits, one start bit and one stop bit. Based on what you have learned about the internal workings of the SCI subsystem, over what range of local baud rate frequencies may we expect the 68HC11 microcontroller to receive data from the peripheral device without any errors?
(Specify frequencies to the nearest tenth of a Hz.)
f (^) min = Hz
f (^) max = Hz
- Design a circuit to interface a microcontroller having (0v, +5v) output voltages with an 18v dc motor having 200Ω winding resistance. Use a BJT with current-snubber network for this purpose. Specify all resistor values. To simplify the problem do not use an optoisolator.
- Why is it useful for a microcontroller to have on-board EEPROM?
- Why is it better to have program code stored in ROM instead of in EEPROM?
- Assume that the 68HC11 microcontroller is configured as the Master device to communicate in serial synchronous fashion with an external 12-bit Analog- to-Digital Converter (ADC). The ADC produces f (^) samp data conversions per second. If one bit is transferred per E clock period Tc = 1 ( 2 MHz), what is the maximum value of f (^) samp that the 68HC11 can possibly keep up with?
fsamp (max) =
- Answer the following questions:
a) What is the advantage of using serial I/O over parallel I/O?
b) What is the advantage of using parallel I/O over serial I/O?
c) What is the purpose for having tri-state outputs on memory chips?
d) What is the disadvantage of using partial address decoding vs. full address decoding for a memory-mapped peripheral?
e) Name one application requiring the use of a bidirectional octal latch:
f) How may an LED be made to appear continuously brighter or dimmer while being driven by a digital signal (0v or 5v at any instant of time)?
- Interface the 68HC12 microcontroller, configured for 16-bit address bus and 8-bit data bus, with an external 4K×8 ROM chip over address range $F000- $FFFF. Use full address decoding logic. Show the connections between this memory chip and the 68HC12 address bus, data bus, R / W and E clock outputs (the 68HC12 reads from memory during the period that E = 1). Include any number of 2-input digital logic gates if needed.
In addition to its address-in and data-out lines, the ROM memory chip has the following control inputs:
CS 1 (^) , CS 2 , CS 3 : one active-low, two active-high chip select lines OE : active-low output enable
Draw the circuit below:
