Download ECE2030 Final Exam: Electrical and Computer Engineering Exam Questions and more Exams Computer Science in PDF only on Docsity!
STUDENT NAME:
(PLEASE PRINT CLEARLY)
REMARKS: 1. All questions should be answered (in the space provided).
- Books and notes may NOT be used.
- Calculators are allowed.
- You are allowed two 8.5”x11” crib sheets.
- The exam is 2 hours and 50 minutes.
DATE: August 1, 2001 TIME: 11:30 p.m. - 2:20 p.m.
Marks:
Total:
Q
Q
Q
Q
Georgia Institute of Technology Department of Electrical and Computer Engineering
Final Exam
ECE2030: Introduction to Computer Engineering
Q
Q
Q
Q
1. SWITCH DESIGN (MAX MARK: 10)
For the two expressions below, create a switch level implementation using nMOS and pMOS transistors. Assume that you also have the complements of each input.
Out 1 = A + B C ( + D ) Out 2 = A BC ( + D ) + E
B
C
B
D
A
V DD
A
Out (^1)
D
C
B
C
B
D
A
V DD
A
Out (^2)
D
C
E
E
3. BOOLEAN SIMPLIFICATION (MAX MARK: 10)
For the following Karnaugh map, derive a simplified product of sums ( POS ) expression. Be sure to circle and list the prime implicants, indicating which are essential. Write the simplified POS expression in the space below.
4. INSTRUCTION SET ARCHITECTURE (MAX MARK: 10)
Suppose that you have a datapath similar to the one discussed in class exept that it has only 8 registers. Also, suppose that you wish to design the processor to be able to handle 80 instruction types (i.e. and, or, andi, add, addi, etc.). Finally, suppse that you require immediate operands to have a range of. Determine the following values for the resulting instruction format that would need to be implemented. For the last two questions, assume the same basic instruction layout as discussed in class exept for the appropriate modifica- tions as required by the above description.
a) What is the minimum number of bits needed to specify the opcode?
b) What is the minimum number of bits needed to specify a register operand?
c) What is the minimum number of bits needed to specify an immediate operand?
d) What is the minimum number of bits needed to specify an R-format instruction?
e) What is the minimum number of bits needed to specify an I-format instruction?
prime implicants
essential? yes no
AB
CD
C
A
B
D D D
B
B
C
A
X=
X=1 1
X=1 1
X=
B + C
B + C + D
A + B + D
A + C + D
F A B C D ( , , , ) = ( B + C ) ( B + C + D ) ( A + C + D )
(POS)
F A B C D ( , , , ) = ( B + C ) ( B + C + D ) ( A + B + D )
or
±16K
5. COMBINATIONAL LOGIC/MEMORY SYSTEMS (MAX MARK: 15)
Consider the relatively complicated memory system on the following page. Note: Each memory chip is numbered (i.e. for the bottom memory chip) so that you can refer to specific chips in your answers.
a) Given the following input, which memory chips are selected (enabled)? Explain.
None of the memory chips will be selected since the MSEL = 0 will cause both outputs of the decoder to be low. These low signals from the decoder will deselect all memory chips.
b) Given the following input, explain what is going to happen to the input data G with each memory chip.
With MSEL = 1 and A[10:0] = 000 0000 1000 , then memory chips , , and will be selected. The signal G will be duplicated, passed through the bank of three AND gates, and supplied to the data bus for the selected memory chips. With the read/write line set for writing, G will be loaded into the memory chips , , and at address 00 0000 1000 for each selected memory chip.
c) When , circle the MUX data inputs that could possibly be passed to F for G = 0 and G = 1.
d) Given the following inputs and current contents of each memory chip at address 01 0000 1000
circle all memory chips that are selected and draw a box around the MUX input that is passed to F.
e) Circle one of the following descriptions that best fits what this memory system does:
- 2Kx1 memory system with triple storage redundancy that uses a majority function during reading in case the memory has been corrupted.
- 2Kx3 memory system with parity bit generation during the write phase and parity bit checking during the read phase of memory access.
- 6Kx1 memory system that operates as an opcode decoder for a single cycle data path unit.
- 2Kx1 memory system that allows a 3-bit parallel load of input data and a serial output of data for serial modem type communications.
- 2Kx3 memory system that allows simultaneous reads and writes to memory.
A[10:0] = 010 1000 0000 MSEL = 0 R/W = 0 G = 1
A[10:0] = 000 0000 1000 MSEL = 1 R/W = 1
R/W = 1
Memory Chip
Address 01 0000 1000 1 0 0 1 1 0
R/W = 0
A[10:0] = 101 0000 1000
MSEL = 1
G = 1
6. STATE MACHINES (MAX MARK: 13)
a) Drawn below is an implementation of a finite state machine (FSM) using negative-edge triggered flip- flops. Write out the Boolean equations for , , and in terms of , and.
b) Develop the state table for these equations.
c) Assuming the flip-flops are initially cleared, complete the following timing diagram for the FSM.
N 1 N 0 Z X P 1 P 0
P 0
Clock
N 0
FF
P 1
Clock
N 1
FF
Z
X
NS 1 = X ⋅ PS 1 NS 0 = PS 1 ⊕ PS 0 Z = PS 1 + PS 0
Present State Input Next State Output
0 1 0 1 0 1 0 1 S 0 or 0 0
P 1 P 0 X Z
S 0 or 0 0 S 1 or 0 1 S 1 or 0 1 S 2 or 1 0 S 2 or 1 0 S 3 or 1 1 S 3 or 1 1
N 1 N 0
S 3 or 1 1 S 3 or 1 1 S 2 or 1 0 S 2 or 1 0 S 2 or 1 0 S 0 or 0 0 S 3 or 1 1 S 1 or 0 1
X
P 1
P 0
Clock
Z
7. SINGLE CYCLE DPU (MAX MARK: 15)
Write a microcode fragment in the table below that implements the MIPS assembly instructions given below. Use the single cycle datapath unit diagram attached at the back of the exam for reference on the control sig- nals and the MIPS assembly reference table for reference on the instructions. For maximum credit, include a description of each microcode operation as well as mark the appropriate “don’t care” inputs with an X.
lw $8, $ sai $14, $8, 0x add $15, $14, $ and $15, $15, $ sw $15, $
Clock Cycle X Y Z rwe imm en
imm va
a en asl a/s
LF
ST
st en
ld en r/w msel Description
1 01010 X 01000 1 0 X 0 XX X XXXX XX 0 1 0 1 R8 = M[R10]
2 01000 X 01110 1 1 0x01 1 01 X XXXX 01 0 0 x 0 R14 = R8 >> 1
3 01110 01000 01111 1 0 X 1 00 0 XXXX XX 0 0 x 0 R15 = R14 + R
4 00111 01111 01111 1 0 X 1 10 X 1000 XX 0 0 x 0 R15 = R15 & R
5 01010 01111 X 0 0 X 0 XX X XXXX XX 1 0 1 1 M[R10] = R
Table 1: Instruction set reference
Instruction Example Meaning
add add $1,$2,$3 R1 = R2 + R
add immediate addi $1,$2,100 R1 = R2 + 100
subtract subi $1,$2,$3 R1 = R2 - R
and and $1,$2,$3 R1 = R2 & R
shift arithmetic immediate sai $1, $2, 0x04 R1 = R2 >> 0x
load word lw $1, $2 R1 = M[R2]
store word sw $1, $2 M[R2] = R
set less than slt $1, $2, $3 if R2 < R3 then R1=0x01 else R1=0x
branch if equal beq $1, $2, offset if R1=R2 then use offset as relative branch
jump register jr $1 jump to address in R
jump and link jal inst_address save PC in $ra and jump to inst_address
Zdi
X do
Y do
X ra Y raZwa
32x
RF
rwe
32 X bus^ Y bus
Z bus
ALU
A B
a en
a/s
ST
LF
asl
Clk
sign extender
im en im va
RAM/ROM
addr
data
TG
TG
st en
ld en
r/w msel
X- register driven onto X bus Y- register driven onto Y bus Z- register written from Z bus rwe - register write enable
X Y Z
im en - immediate register enable
For all enables, 0=disable and 1=enable
a en - ALU enable LF - 4 bit logical function
A B
Logical Function LF LF 0 LF 1 LF 2 LF 3
ST - 2 bit shift type
Shift Types 00 = Logical 01 = Arithmetic 10 = Rotate
Shift Direction (B on ALU) positive B = shift right negative B = shift left
im va - immediate value st en - store enable ld en - load enable
a/s - add or subtract (add=0, sub=1) asl - arithmetic unit, shift unit, logical unit select
r/w - memory read/write (read=0,write=1) msel - memory select
asl 00 - select arithmetic unit 01 - select shift unit 10 - select logical unit
