Februar 25, 2009 page 1 S. Derenzo
Solutions for Midterm #1 - EECS 145M Spring 2009
1.1 Edge-triggered D-type flip-flop:
one digital data input
one digital clock input
one digital data output
the output is set equal to the input on every rising edge of the clock
1.2 Transparent latch:
one digital data input
one digital gate input
one digital data output
the output is equal to the input when the gate signal is high
the output does not change when the gate signal is low
1.3 Sample and hold amplifier
one analog data input
one digital control input
one analog data output
the output is equal to the input when the control is set to sample mode
the output does not change when the control is set to hold mode
1.4 Tri-state buffer
one digital data input
one digital “output enable” input
one digital data output
the output is equal to the input when the “output enable” signal is low
the output is high impedance when the “output enable” signal is high
1.5 A/D converter (12 bit)
one digital “start conversion” input
one analog input
one digital “data available” output
one 12-bit digital output
Note: Vref+ and Vref– are also needed, but no points were deducted if these were omitted
2 Error 1: clock input is pulsed in step 2 before input is asserted. Fix by asserting the input
before providing the clock edge (reverse second part of step 2 and first part of step 3)
Error 2: the external circuit never resets “input data available” to FALSE so that step 4 is
executed and the program reads the flip-flops over and over again, without regard for when
the external circuit asserts and clocks new data. Fix by adding a step 6 so that the external
circuit sets “input data available” FALSE when it detects “ready for input data” FALSE
[3 points off for only reversing steps 2 and 3- this sets “input data available” before the flip-
flops are clocked and could cause the program to read data too soon]
[10 points off for missing either error]
