ECE 598 SV
Formal Hardware/SoC Verification
Lecture 3
Hardware Design Cycle
Specification
RTL
Gates
Transistors
Physical Design
Testing
Documentation/C/C++
P,A,T
P,A,T
Logic Sythesis
High level
Sythesis
HDL: Cycle-accurate
Concurrent
Non-terminating
Concurreny in hardware involves a notion of non-determinism, as there is no apriori
scheduling of the concurrent events. No interleaving/semaphores in this context.
RTL and Logic Synthesis stages of the cycle can be highly manual and requires
tweaking. Formal verification is needed the most here, to check if functionality is
maintained.
In Logic Synthesis, Equivalence Checking is commonly used.
Model Checking (1981) is almost never used in its explicit state-space form, eg. Intel
uses STE (Symbolic Trajectory Evaluation) for its microprocessors.
