ECE385
DIGITAL SYSTEMS LABORATORY
DIGITAL
SYSTEMS
LABORATORY
Lecture
Introduction to VHDL
© Janak H Patel
©
Janak
H
.
Patel
Department of Electrical and Computer Engineering
Universit
y
of Illinois at Urbana-Cham
p
ai
g
n
y
pg
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Hardware Description Languages - Lecture Slides | ECE 385, Lab Reports of Electrical and Electronics Engineering
Material Type: Lab; Professor: Patel; Class: Digital Systems Laboratory; Subject: Electrical and Computer Engr; University: University of Illinois - Urbana-Champaign; Term: Unknown 1989;
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ECE
DIGITAL SYSTEMS LABORATORYDIGITAL
SYSTEMS LABORATORY
Lecture
Introduction to VHDL
© Janak H Patel©^ Janak H. Patel
Department of Electrical and Computer EngineeringUniversity of Illinois at Urbana-Champaign
y^
p^ g
Topicsp
z^ Programmable Logic^
PLAs PLDs FPGAs PLAs
, PLDs, FPGAs
z^ Design Description Languages z^ I^
t^ d^
ti^
t^ VHDL
z^ Introduction to VHDL^
Logic Value System of VHDLE tit Entity ArchitectureC^
S
^ Concurrent Statements
PLDs and FPGAs
z^ Speed^
PLDs give predictable timing and give higher PLDs
give predictable timing, and give higher
system clock frequency FPGA clock frequency is design dependent and
q^
y^
g^
p
usually much slower than PLDs
z^ Size^
PLDs can accommodate up to 10,000 gates FPGAs can accommodate up to 25 million gates
z^ D^
i^ fl
ibilit
z^ Design flexibility^
FPGAs often come with large memory andpredefined function unitspredefined function units
z^ Manufacturers^
Xilinx, Altera, Lucent, Cypress, Lattice
Xilinx, Altera, Lucent, Cypress, Lattice
Hardware Description Languages
p^
g^
g
z^ Two Widely Used Languages^
Verilog HDL Verilog
HDL
^ C-language like syntax, easy to learn VHDL ^ VHSIC Hardware Description Language ^ VHSIC - Very High Speed Integrated Circuits ^ Follows the structure of ADA programmingLanguage ^ Originally intended as a Simulation Language for^ Originally intended as a Simulation Language forvery large systems ^ Very Strongly Typed Language, for example,
bit
t^ “0011”
d^
i t^
‘3’^
t^
il
vector
and^
integer
‘3’^ are not easily
interchangeable
^ Verilog and VHDL each have about 50% share of
^ Verilog and VHDL each have about 50% share ofthe commercial user base
Entities and Architectures
z^ Entity^
External View
: Pin
-Out description, Interface
^ External View: Pin Out description, Interfacedescription, Input-Output Port definition etc. z Architecture ^ Internal View^ ^
Structural Description - e.g. Gates and wiresB h^
i^ l D
i ti
f^ ti
d
^ Behavioral Description - e.g. functions and processes,RTL description, if-then-else, Add, Subtract
ENTITY
mux
Din
ARCHITECTURE
sel
Dout
4-to-1 Multiplexer (behavioral)
p^
(^
library IEEE;
--^ libraries needed for
use IEEE.std_logic_1164.all;
simple logic functions
entity mux isport (sel: in std_logic_vector(1 downto 0);
Din: in std logic vector (3 downto 0);Din: in std_logic_vector (3 downto 0);Dout: out std_logic); end entity mux;architecture my_mux_behavior of mux isbegin
--^ all comments are preceded by two dashes
Dout <= Din(3) when sel=“11” else
first evaluate this
Dout <
Din(3) when sel
else
first^ evaluate this
Din(2) when sel=“10” else
next evaluate this
Din(1) when sel=“01” else
then evaluate thish^
l^
h
Din(0) when sel=“00” else
then evaluate this
‘X’;
--^ if all fails then X
end architecture my mux behavior;
y_^
_^
(“when
4-to-1 Multiplexer using gates
p^
g g
Din(3)
s0bar s1bar Din(2)Di^ (1)
Dout =
Din(1) Din(0)
Din(3)●
sel(1)●
sel(0) + Din(2)●
sel(1)●
s0bar + Din(1)●
s1bar●
sel(0) + ( )^
( ) Din(0)●
s1bar●
s0bar
sel(1)
sel(0)
architecture
structure
of^ mux
is
signal
s0bar,
s1bar;
std_logic;
--^ internal
signals
b^ ibegins0bar
<=^ not(sel(0)); s1bar <=^ not(sel(1)); Dout^ <=^ (Din(3)
and^ sel(1)
and^ sel(0))
or
(Din(2)
and^ sel(1)
and^ s0bar)
or
(Din(2)
and^ sel(1)
and^ s0bar)
or
(Din(1)
and^ s1bar and^ sel(0))
or
(Din(0)
and^ s1bar and^ s0bar);
end^ architecture
structure;
4-to-1 Multiplexer (Structural)
p^
(^
library IEEE;use IEEE.std_logic_1164.all;entity mux isport (sel: in std_logic_vector(1 downto 0);
Din: in std logic vector (3 downto 0);Din: in std_logic_vector (3 downto 0);Dout: out std_logic); end entity mux;architecture structure of mux issignal s0bar, s1bar; std_logic; -- internal signalsbegin
--^ following three are concurrent signal assignments (CSAs) g^
f^
g^
g^
g^
(^
s0bar <= not(sel(0)); --
these are not executed sequentially
s1bar <= not(sel(1)); --
order of these CSAs is unimportant!
Dout <= (Din(3) and sel(1) and sel(0))or Dout <
(Din(3) and sel(1) and sel(0))or(Din(2) and sel(1) and s0bar) or(Din(1) and s1bar and sel(0)) or(Din(0) and s1bar and s0bar); (Din(0)
and s1bar and s0bar);
end architecture structure;
A^ Bit-Serial Logic Unit
g
F2-F
A in^
A_out
One-bit wideLogic Unit“compute” A_inB_in^
F_A_B compute
B_out
entity compute isPort ( F : in std logic vector(2 downto 0);Port ( F : in std_logic_vector(2 downto 0);
A_In, B_In : in std_logic;A_Out, B_Out : out std_logic;F A B
o t std logic) F_A_B : out std_logic); end entity compute;
Behavioral of Logic Processor
g
architecture Behavioral of compute isbeginwith F selectF_A_B <= A_In and B_In when "000",
A In or B In when "001",_^
_^
A_In xor B_In when "010",'1' when "011",A In nand B In when "100",A_In nand B_In when
A_In nor B_In when "101",A_In xnor B_In when "110",'0' when others;
must be included
'0' when others; --
must
be included
A_Out <= A_In;B_Out <= B_In;end architecture Behavioral;
Sequential Circuit Example
q^
p
entity up_down_counter is
t ( lk
bl^
d^
i^ td l
i
port (clk, enable, up_down : in std_logic;
asynch_clr: in std_logic;Q: out std logic vector(7 downto 0);Q: out std_logic_vector(7 downto 0); end entity;
8 bit U
D^
C^
t
enableup down
8 -bit Up-Down Counter
asynch_clr
p_ clk
Q(7) Q(6).....
Q(1)Q(0)
Counter Behavior
architecture counter_behavior of up_dn_counter issignal count: std_logic_vector(7 downto 0);Begin
count
is an internal signal to this process
Begin
-- count
is^ an internal signal to this process
process(clk, asynch_reset)
--^ sensitivity list
beginif (asynch reset=‘1’) then count <= “00000000”;if (asynch_reset= 1 ) then count <=
elsif (rising_edge(clk)) then –
synchronous state transitions
if (enable=‘1’) thenif (up down=‘1’) then count <= count+”00000001”;if (up_down
1 ) then count <
count+ 00000001 ; else count <= count-”00000001”;
end if;end if;
-- ‘end if’
is not permitted here to match
‘elsif’
end if;end process;p Q <= count;end architecture counter_behavior; Note: We cannot use
“Q <= Q + 1”
since
Q^ is defined as output only
Counter Behavior-
architecture counter_behavior of up_dn_counter isbeginprocess(clk, synch_reset)
--^ sensitivity list
beginif (rising_edge(clk) then
_
if(synch_reset=‘1’) then Q <= “00000000”;elsif (enable=‘1’) then
notice no
‘ e’^ in
‘ elsif
if (up down=‘1’) then Q <= Q + ’1’( p_
)^
Q^
Q
else Q <= Q - ’1’;
end if;-- “end if
”^ is not permitted here to match the
“elsif
end if
is^ not permitted here to match the
elsif
end if;end if; --
notice it is
‘ end if’
not^
‘endif’
end process;end process;end architecture counter_behavior;
4-Bit Shift Register
g
entity reg_4 isPort (Shift_In, Load, Shift_En, Clk
: in std_logic;
D : in std_logic_vector(3 downto 0);Shift Out : out std logic;
_^
_^ g
Data_Out : out std_logic_vector(3 downto 0); end entity reg_4;
4 D
4-Bit Register^ “reg 4
Shift_InLoad
Data_OutShift Out 4
reg_
LoadShift_EnClk
Shift_Out