Hardware Description Languages - Lecture Slides | ECE 153B, Lab Reports of Electrical and Electronics Engineering

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• VHDL --- Part I ECE 153B --- Jan 29,

Hardware Description Languages
^ HDLs support top-down digital systems design

Functional Design

Register Transfer level Design

Requirements^ Logic Design Circuit Design Physical Design

…… behavioral simulation…… RTL simulation…… logic sim, verification, fault sim…… timing & circuit simulation…… DRC, LVS, timing simulation …

Behavioral & Structural Descriptions
^ digital systems are about signals

(0 vs. 1)

^ made from components

, e.g.

^

gates, FF’s, muxes, decoders, counters
^ components interconnected by wires^ 

transform inputs

into outputs

Consider a Half-Adder
a ,

b^ are inputs
^ sum

,^ carry

are outputs

^ xor

,^ and

are components ^ with internal functions that transform their inputs to their outputs
interconnecting everything are wires

xor and

sum

sum carry

a b

IEEE 1164 ... 9-valued logic system

don’t care

weak 1

H

weak 0

L

weak unknown

w

high impedance (floating)

Z

forcing 1

forcing 0

forcing unknown

x

uninitialized

U

Interpretation

Value

• Known as “std_ulogic” or “std_ulogic_vector” …. ‘u’ for ‘unresolved’

Half-Adder re-written using std_ulogic entity

half_adder

is

port^

(^ a,^

b^ :^ in

std_ulogic; sum,^

carry

:^ out

std_ulogic

);

end^ half_adder;
^ VHDL is case insensitive for keywords and identifiers
^ Inputs and outputs are referred to as ports
^ Ports are special programming objects & also they are signals
^ Each must be declared to be a certain type, in this case “std_ulogic” (a 9-valued signal type)^ 

Another possibility is bit_vector – a 1-dimensional array or vector of bits

xor and

sum

sum carry

a b

Entities and Architectures entity

mux is port^ (^ I0,

I1, I2, I^ :^ in std_ulogic_vector

(^ downto

0);

sel^ :^ in std_ulogic_vector (1 downto

0);

Z^ : out

std_ulogic_vector

(^ downto

0)^ );

end^

mux; architecture

behav of

mux is

-- place declarations here (note that -- introduces a line comment)begin -- description of behavior hereend^

behav;

^ Once we have described an entity’s interface ports,

^ we can describe its internal behavior

^ Every VHDL design must have at least one entity/architecture pair

Some Common Data Types

Chardata <= ‘x’;

‘a’,’b’,’2’,’$’

character

msg <= “MEM:” & addr;

array of characters

string

Q <= ‘1’ after 6 ns;

7ns, 100ps

time

v1 = v2 / 5.3;

1.0, -1.27E

real

count <= count + 2;

integer

EQ <= True;

True, False

boolean

data <= “00010110”;

1-D array of bits

bit_vector

Q <= ‘1’;

bit

Example

Values

Type

Concurrent signal assignments -- CSAs architecture

concur_behav of

half_adder is

begin sum <= (a xor

b) after

5 ns

carry <= (a and

b) after

5 ns

end^

concur_behav;

^ We can use CSAs to specify behavior ^ If an event (signal transition) occurs on a signal on the rhs of a CSA,

^ the expression is evaluated and new values are scheduled for a time in the futureper the optional after

clause

^ The order of CSAs is not significant. They are concurrent

A 4-to-1 multiplexer … when/else entity

mux is port^ (^ A,

B,^ C,^ D :

in^ std_ulogic;

sel^ :^ in std_ulogic_vector (1 downto 0); Y^ : out

std_ulogic);

end^

mux; architecture

m1 of

mux is

begin^ Y <= A when

(sel = "00") else B when

(sel = "01") else C when

(sel = "10") else D when

(sel = "11");

end^

m1;

sumA

mux

B C D

Y

sel

called a ‘conditional signal assignment’

• aka a ‘when/else’ statement

Process statement architecture

arch_name of

entity_name is

begin^ process_name: process

( sensitivity list ) local declaration(s);

begin sequential stmt;sequential stmt;

end^

process

end^

• primary means by which sequential arch_name;

circuits are described

Any event (change) in any of thesesignals causes execution of theprocess^ Simulated time stands still duringsequential

execution of these

statements. There is another kind of process;without

any sensitivity list. It uses

wait

until

(condition) or

wait

for^ (condition) statements

Concurrent vs. Sequential Execution Concurrent

(between begin/end in architecture)
^ everything happens “at once”
^ no significance to statement order

begin

begin statement statement statement statement^ end

statement statement statement

end

Sequential (between begin/end in a process

^ statements happen in strict sequence

Elements of the language
Signals^ ^

Objects that connect concurrent elements  All ports

are signals

^ Variables^ 

Objects used to store intermediate values between sequential statements  Only allowed in processes & functions …. always local

^ Constants^ 

Assigned a value once (when declared) …. do not change^
^

Constant count_limit : integer

^ Constant msg : string

:= “This is a string”;

^ Constant myaddr : bit_vector

(15 downto

0) := X”F0F0”;

^ Literals

(next slide)

Literals in VHDL
Explicit data values that are assigned to objects or used in expressions
Character literals --- 1 char ASCII values enclosed in single quotes^ ^

‘A’, ‘$’, ‘g’

^ String literals --- one or more ASCII characters in double quotes^ 

“testing, 1-2-3” ,

“This is a string of characters --- i.e. a string literal”

^ Bit-string literals --- special string literals to represent binary, octal, hex^ 

B”01101111”

---- 8-bit binary literal

^ O”7602” ------------ 3 x 4 = 12 bits in octal ^ X”1CF2” ------------- 16-bit hexadecimal literal
Numeric literals --- decimal integers and reals ^ 5.

1.6E

2.45E-

^ Based literals^ 

16#FFCC#

2#101.00#E

^ Physical literals – representing physical quantities like time, voltage, current, distance^ 

300 ns, 900 ps, 40 ma,

16 v

-- always a numeric part and a unit specification