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CS 152: Computer Architecture

and Engineering

Lecture 5

Hardware Description Languages,

Multiple and Divide

Hardware Representation Languages :

Block Diagrams: FUs, Registers, & Dataflows

Register Transfer Diagrams: Choice of busses to connect FUs, Regs

Flowcharts

State Diagrams

Fifth Representation “Language”: Hardware Description Languages

E.G., ISP'

VHDL

Verilog

Descriptions in these languages can be used as input to

simulation systems

synthesis systems

Representation Languages

Two different ways to describe

sequencing & microoperations

hw modules described like programs

with i/o ports, internal state, & parallel

execution of assignment statements

“software breadboard”

generate hw from high level description

"To Design is to Represent"

Levels of Description

Architectural Simulation

Functional/Behavioral

Register Transfer

Logic

Circuit

Models programmer's view at a

high level; written in your favorite

programming language

More detailed model, like the

block diagram view

Commitment to datapath FUs,

registers, busses; register xfer

operations are clock phase

accurate

Model is in terms of logic gates;

higher level MSI functions

described in terms of these

Electrical behavior; accurate

waveforms

Schematic capture + logic simulation package

Special languages + simulation systems for describing the inherent

parallel activity in hardware

Less

Abstract

More

Accurate

Slower

Simulation

Verilog and VHDL

(Hardware Description Languages)

 Goals:

• Support design, documentation, and simulation of hardware
  • Verilog is C like, VHDL is ADA/Pascal like
• Digital system level to gate level
• “Technology Insertion”

 Concepts:

• Verilog Module/VHDL Design Entity
• Time-based execution model.

Module/Design Entity ==

Logical entity implemented

by a piece of hardware

e.g., logic gate, 32-bit adder,

memory subsystem

Interface == External

Characteristics

Architecture (Body ) ==

Internal Behavior

or Structure Docsity.com

Structural Descriptions

 Instances of “wired” lower level module within

the current module

fulladd f1 (cin0, a0, b0, sum0, cout0)

fulladd f2 (cout0, a1, b1, sum1, cout2)

f

a0 b

cin

sum

cout

f

a1 b

sum

cout

Verilog Operators

 Operators borrowed from C programming language

• • • /

= < <= ! && ||

== != ?: {} % === !== ~ & | << >>

Arithmetic Relational Logical Logical equality Conditional Concatenate Modulus Case equality Bit-wise Shift

Clocking and Delays

 Unlike conventional programs, not a serial model of execution

 Global variable designates simulation time

• Multiple events scheduled for execution at the same time
• Execute all events for the current simulation time (in essentially a random order) before advancing to the next simulation time
• New events generated as a by-product of execution and are added to the simulation pending queue

module repeat_loop (clock); input clock; initial begin repeat (5) @(posedge clock); $stop; end endmodule

Initial: execute at start of sim Wait for 5 positive clock edges Stop simulation

Clocking and Delays

Synchronous: #expression – suspend execution for indicated time Asynchronous: @expression – suspend execution until event occurs Level: wait (expression) – suspend execution until expression true

module time_control; reg[1:0] r; initial #70 $stop; initial begin : b1 //named block b #10 r = 1; //wait for 10 time units #20 r = 1; //wait for 20 time units #30 r = 1; //wait for 30 time units end initial begin : b2 //named block b #5 r = 2; //wait for 5 time units #20 r = 2; //wait for 20 time units #30 r = 2; //wait for 30 time units end always @r begin $display (“r= %0d at time %0d”, r, $time); end endmodule

MIPS Arithmetic Instructions

Instruction Example Meaning Comments

add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder Hi = $2 mod $ divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder Hi = $2 mod $ Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo

MULTIPLY (unsigned)

 Paper and pencil example (unsigned):

Multiplicand 1000 Multiplier 1001 1000 0000 0000 1000 Product 01001000

 m bits x n bits = m+n bit product

 Binary makes it easy:

• 0 => place 0 ( 0 x multiplicand)
• 1 => place a copy ( 1 x multiplicand)

 Four versions of multiply hardware & algorithm:

• Successive refinement

Carry Save Addition of Four Integers

 Add Columns first,

then rows!

 Can be used to

reduce critical path of multiply

 Example: 53 bit

multiply (for floating point):

• At least 53 levels with naïve technique
• Only 9 with Carry save addition!

Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3) Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3) Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3)

0

C 2

Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3) Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3) Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3)

S 4 S 3 S 2 S 1 S 0

Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3) Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3)

0

Carry Save Adder3=>

I 1 I (^2)

S 1 S (^0)

I (^3)

B 2 A 2 C 1 B 1 A 1 C 0 B 0 A 0

D 2 D 1 D 0

How Does It Work?

 At each stage shift A left ( x 2)

 Use next bit of B to determine whether to add in shifted multiplicand

 Accumulate 2n bit partial product at each stage

B 0

A 3 A 2 A 1 A 0

A 3 A 2 A 1 A 0

A 3 A 2 A 1 A 0

A 3 A 2 A 1 A 0

B 1

B 2

B 3

P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0

0 0 0 0 0 0 0

Multiply Algorithm Version 1

 Product Multiplier Multiplicand

3. Shift the Multiplier register right 1 bit.

Done

Yes: 32 repetitions

2. Shift the Multiplicand register left 1 bit.

No: < 32 repetitions

1. (^) Test Multiplier

Multiplier0 = 1 Multiplier0 = 0

1a. Add multiplicand to product &

place the result in Product register

32nd repetition?

Start

Observations on Multiply Version 1

 1 clock per cycle => ≈ 100 clocks per multiply

• Ratio of multiply to add 5:1 to 100:

 1/2 bits in multiplicand always 0

=> 64-bit adder is wasted

 0’s inserted in left of multiplicand as shifted

=> least significant bits of product never

changed once formed

 Instead of shifting multiplicand to left, shift

product to right?