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ECE
DIGITAL SYSTEMS LABORATORY
© Janak H. Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Experiment 9
PS/2 Keyboard and VGA
Interface
Today’s Topics
z Experiment 9
PS/2 Keyboard Description
Hardware interface for inputting from a Keyboard
VGA Description
Hardware interface for outputting to a VGA Monitor
DE2 Development Board
PS/
Keyboard
and Mouse
connector
VGA
Connector
Top view
PS/2 keyboard/mouse
z The PS/2 mouse and keyboard implement a
bidirectional synchronous serial protocol. It uses two
lines: ps2clk and ps2data
z The bus is "idle" when both lines are high (open-
collector). This is the only state where the
keyboard/mouse is allowed to begin transmitting
data. The host has ultimate control over the bus and
may inhibit communication at any time by pulling the
Clock line low.
z We will only use unidirectional communication for
Experiment 9: From Keyboard to host (DE2 Board)
For more information on PS/2 protocol see:
http://www.computer-engineering.org/
PS/2 Serial Protocol
z The keyboard/mouse always generate the clock signal.
All data is transmitted one byte at a time and each byte is
sent in a frame consisting of 11 bits. These bits are:
1 start bit. This is always 0.
8 data bits, least significant bit first
1 parity bit (odd parity) You can ignore it for Expt. 9.
1 stop bit. This is always 1.
z A data frame is exactly 11 trailing edges of the psClk
Between successive frames there can be arbitrary idle period
idle idle
psClk frequency is between 10KHz to 16.7KHz
Keyboard Scan Codes
z Most key strokes send three bytes (11 bits each)
A byte of Make-Code (also called Scan-Code)
Two bytes of Break-Code (release key)
A key code xy is sent as 3 bytes: xy-F0-xy
Key “E” is Hex 24–F0–
Key “7” is Hex 3D–F0–3D
“Extend” key code xy is 5 bytes : E0-xy-E0-F0-xy
Key “↑” is Hex E0-75-E0-F0-
Key “←” is Hex E0-6B-E0-F0-6B
F0 byte is always one before the LAST byte
z For a complete scan code set see
http://www.computer-engineering.org/ps2keyboard/scancodes2.html
S 1B F0,1B ENTER 5A F0,5A KP 0 70 F0,
R 2D F0,2D APPS E0,2F E0,F0,2F KP. 71 F0,
Q 15 F0,15 R ALT E0,11 E0,F0,11 KP EN E0,5A E0,F0,5A
P 4D F0,4D R GUI E0,27 E0,F0,27 KP + 79 F0,
O 44 F0,44 R CTRL E0,14 E0,F0,14 KP - 7B F0,7B
N 31 F0,31 R SHFT 59 F0,59 KP * 7C F0,7C
M 3A F0,3A L ALT 11 F0,11 KP / E0,4A E0,F0,4A
L 4B F0,4B L GUI E0,1F E0,F0,1F NUM 77 F0,
K 42 F0,42 L CTRL 14 FO,14 R ARROW E0,74 E0,F0,
J 3B F0,3B L SHFT 12 FO,12 D ARROW E0,72 E0,F0,
I 43 F0,43 CAPS 58 F0,58 L ARROW E0,6B E0,F0,6B
H 33 F0,33 TAB 0D F0,0D U ARROW E0,75 E0,F0,
G 34 F0,34 SPACE 29 F0,29 PG DN E0,7A E0,F0,7A
F 2B F0,2B BKSP 66 F0,66 END E0,69 E0,F0,
E 24 F0,24 \ 5D F0,5D DELETE E0,71 E0,F0,
D 23 F0,23 = 55 FO,55 PG UP E0,7D E0,F0,7D
C 21 F0,21 - 4E F0,4E HOME E0,6C E0,F0,6C
B 32 F0,32 ` 0E F0,0E INSERT E0,70 E0,F0,
A 1C F0,1C 9 46 F0,46 [ 54 FO,
KEY MAKE BREAK KEY MAKE BREAK KEY MAKE BREAK
Keyboard Scan Set 2 (part 1)
Keyboard Scan Set 2 (part 2)
-NONE-
E1,14,77,
E1,F0,14,
F0,
8 3E F0,3E PAUSE
7 3D F0,3D SCROLL 7E F0,7E / 4A F0,4A
. 49 F0,
E0,F0,
7C,E0,
F0,
E0,12,
E0,7C
PRNT
SCRN
6 36 F0,
5 2E F0,2E F12 07 F0,07 , 41 F0,
4 25 F0,25 F11 78 F0,78 ' 52 F0,
3 26 F0,26 F10 09 F0,09 ; 4C F0,4C
2 1E F0,1E F9 01 F0,01 ] 5B F0,5B
1 16 F0,16 F8 0A F0,0A KP 9 7D F0,7D
0 45 F0,45 F7 83 F0,83 KP 8 75 F0,
Z 1A F0,1A F6 0B F0,0B KP 7 6C F0,6C
Y 35 F0,35 F5 03 F0,03 KP 6 74 F0,
X 22 F0,22 F4 0C F0,0C KP 5 73 F0,
W 1D F0,1D F3 04 F0,04 KP 4 6B F0,6B
V 2A F0,2A F2 06 F0,06 KP 3 7A F0,7A
U 3C F0,3C F1 05 F0,05 KP 2 72 F0,
T 2C F0,2C ESC 76 F0,76 KP 1 69 F0,
KEY MAKE BREAK KEY MAKE BREAK KEY MAKE BREAK
Hardware Block Diagram
Scan Register
ps2clk
ps2data
Bit-bucket!
Combinational Logic
Code Mapper
This design also applies to
any Serial to Parallel conversion
d7 d
stop parity
bit bit
7-Segment
Hex displays
Signal
Conditioning
and
synchronizing
Buffer
start
bit
To other logic
requiring keyboard
inputs
A word about Clocks
z DE2 default System clock is 50MHz (pin N2)
This clock can be divided using counters and
taking the output directly from a counter flip-flop as
the divided clock signal
Any other data signal from combinational logic if
used as clock will result in unreliable design and
create synchronization problems
External Clocks as Data Input
z External Clocks such as ps2clk can make ps2data
capture simple but at the cost of complications
arising from two unrelated clocks (do not use!)
z A better design will use only one clock and treat
ps2clk as a data waveform that can be decoded
for rising and falling edge as below
D Q
clk
DFF
D Q
DFF
Pin N
(50MHz)/512 ≈ 100kHz
Pin D
~10kHz
ps2clk Q2Q1^ psClk
1 0 Falling Edge
0 1 Rising Edge
0 0 Level 0
1 1 Level 1
Caution: As given, DFF1 samples the psClk waveform at 5,000 samples for each psClk period.
To reduce possible errors when the falling edge of psClk is noisy, one should reduce the sampling
rate. Divide the 50MHz by say 512 and use the divided clock for DFF1 and 2 and Shift operation.
Hints for VHDL code
z Scan shift register can be inferred by the
synthesizer if you use clock-edge and describe
shift operation on a signal bit-vector
In other words, you need not create an entity
z Map from one code to another can be
accomplished by either
“select” – “when” construct outside a process, or in
“case” – “when” construct inside a process
z Make sure to account for F0 bytes when looking
for keystrokes
Most common design error is “Framing Error”
where incorrect byte is identified as the first byte
Keyboard-Ball-VGA interface
Assume the Keyboard code uses a flip-flop NewKey to indicate that a new
key was pressed and the key code has been obtained.
For the protocol interface Assume a DataReady flip-flop and a DataBuffer
Initialize: DataReady <= ‘0’;
Interface: If ((rising_edge(clk) and (DataReady=‘0’) and (NewKey=‘1’))
then
DataBuffer <= NewKeyCode;
DataReady <= ‘1’; -- signal Ball that a new command is issued
NewKeyAck <= ‘0’; -- tell KeyBoard code that key has been consumed,
endif; -- ok to de-assert NewKey
BALL: if ((rising_edge(clk)) and (DataReady=‘1’))
then
DataReadyAck <=‘0’; -- signal Interface that command has been
endif; -- consumed
