Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Questions from a midterm exam in a digital computers: organization and logical design course. The questions cover topics such as logic diagrams, boolean algebra, simulation output analysis, and vhdl module implementation. Students are required to answer questions related to drawing logic diagrams, simplifying boolean expressions, analyzing simulation output, and finding the simplest equivalent expression using boolean algebra.
Typology: Exams
1 / 7
This page cannot be seen from the preview
Don't miss anything!
(do not simplify the expression first).
How many transistors are needed to implement this expression in CMOS technology?
( A ′ + B + C ). List all its other minterms and maxterms.
section 1 of the course notes. The portions of the output corresponding to four different instructions are outlined. Identify the instructions that are being executed. Give the name of the instruction (e.g. direct load, branch-on-positive) and its complete numeric representation. Note that some parts of the simulation output have been blanked out.
0000 halt execution 0001 negate the value in the ACC 1xxx change the value of the ACC to xxx 2xxx load the contents of memory location xxx into the ACC 3xxx load the ACC from the memory location whose address is stored in memory location xxx 4xxx store the value in the ACC in memory location xxx 5xxx store the value in the ACC in the memory location whose address is stored in location xxx 6xxx change the value of the PC to xxx 7xxx change the value of the PC to xxx if ACC = 0 8xxx change the value of the PC to xxx if ACC > 0 9xxx change the value of the PC to xxx if ACC < 0 Axxx add the value in memory location xxx to the ACC
below. Use simple gates only. library IEEE; use IEEE.std_logic_1164.all;
entity foo is port ( A: in std_logic; B: in std_logic_vector(3 downto 0); X: out std_logic_vector(2 downto 0)); end foo; architecture a1 of foo is signal Z: std_logic_vector(2 downto 0); begin process(A, B, Z) begin Z(0) <= A xor B(0); for i in 1 to 2 loop Z(i) <= B(i) and Z(i-1); end loop; end process; X(2) <= Z(0); X(1 downto 0) <= Z(2 downto 1); end a1;
function of the carry input C in and data inputs A 0 , A 1 ,... , A i.
Show that the circuit below implements a 4 bit increment function.
If a CMOS NAND or NOR gate has a delay of 2 ns and an inverter has a delay of 1 ns, how much faster is a 64 bit version of this circuit than the ripple-carry circuit discussed in class? Explain.
S (^0) S 1
A 0 A 1
S 2 S 3
A (^2) A 3
C out
C in
S (^0) S 1
A 0 A 1
S 2 S 3
A (^2) A 3
C out
C in
circuit, or a Moore model circuit? Draw a state diagram that corresponds to the state table.
