Machine Information and Scheduling in Compiler Design - Prof. Scott Mahlke, Study notes of Electrical and Electronics Engineering

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EECS 583 – Class 13 Instruction Scheduling

University of Michigan February 21, 2005

• 1 -

Reading Material^ Y

Today’s class

»^ “Machine Description Driven Compilers for EPIC Processors”,B. Rau, V. Kathail, and S. Aditya, HP Technical Report, HPL-98-40, 1998.

Y^

Material for the next lecture^ »^

“Three Architectural Models for Compiler-ControlledSpeculative Execution”, P. Chang et al., IEEE Transactions onComputers, Vol. 44, No. 4, April 1995, pp. 481-494.

• 3 -

Machine Information^ Y

Each step of code generation requires knowledge of themachine

»^ Hard code it? – used to be common practice »^ Retargetability, then cannot

Y^

What does the code generator need to know about thetarget processor?^ »^

Structural information?^ y^

No

»^ For each opcode

y^ What registers can be accessed as each of its operands y^ Other operand encoding limitations

»^ Operation latencies

y^ Read inputs, write outputs

»^ Resources utilized

y^ Which ones, when

• 4 -

Machine Description (mdes)^ Y

Elcor mdes supports very general class of EPICprocessors

»^ Probably more general than you need

»^ Weakness – Does not support ISA changes like GCC

Y^

Terminology^ »^

Generic opcode^ y^

Virtual opcode, machine supports k versions of it y ADD_W

»^ Architecture opcode or unit specific opcode or sched opcode

y^ Specific assembly operation of the processor y^ ADD_W.0 = add on function unit 0 Y^

Each unit specific opcode has 3 properties^ »^

IO format » Latency » Resource usage

• 6 -

Latency Information^ Y^

Multiply takes 3 cycles^ »^

No, not that simple!!! Y^

Differential input/outputlatencies^ »^

Earliest read latency for eachsource operand » Latest read latency for eachsource operand » Earliest write latency for eachdestination operand » Latest write latency for eachdestination operand Y^

Why all this?^ »^

Unexpected events may makeoperands arrive late or beproduced early

Y^

Compound op: part may finishearly or start late

Y^

Instruction re-execution by^ »^

Exception handlers » Interupt handlers Y^

Ex: mpyadd(d1, d2, s1, s2, s3)^ »^

d1 = s1 * s2, d2 = d1 + s

s^

s2 d

s

E/L

s1: 0/

s2: 0/

s3: 2/

d1: 2/3 d2: 2/

d

• 7 -

Memory Serialization Latency^ Y

Ensuring the proper ordering of dependent memoryoperations Y Not the memory latency

»^ But, point in the memory pipeline where 2 ops are guaranteed tobe processed in sequential order

Y^

Page fault – memory op is re-executed, so need^ »^

Earliest mem serialization latency » Latest mem serialization latency

Y^

Remember^ »^

Compiler will use this, so any 2 memory ops that cannot beproven independent, must be separated by mem serializationlatency.

• 9 -

Resources^ Y

A machine resource

is any aspect of the target processor

for which over-subscription is possible if not explicitlymanaged by the compiler^ »^

Scheduler must pick conflict free combinations

Y^

3 kinds of machine resources^ »^

Hardware resources

are hardware entities that would be occupied

or used during the execution of an opcode^ y^

Integer ALUS, pipeline stages, register ports, busses, etc.

»^ Abstract resources

are conceptual entities that are used to model

operation conflicts or sharing constraints that do not directlycorrespond to any hardware resource^ y^

Sharing an instruction field

»^ Counted resources

are identical resources such that k are required

to do something^ y^

Any 2 input busses

• 10 -

Reservation Tables^ For each opcode, the resources^ used at each cycle relative to its^ initiation time are specified in the^ form of a table^ Res1, Res2 are abstract resources^ to model issue constraints

Res

ALURes

ResultbusMPY

X^

X

X

relative^ time

0 1 Integer add

Res

ALURes

ResultbusMPY

X^

X^

X

X

Res

ALURes

ResultbusMPY

X^

X X

X

relative^ time

relative^ time

Load, uses ALU for addr calculation, can’t issue load with add or multiply

Non-pipelined multiply

• 12 -

Data Dependences^ Y

Data dependences

»^ If 2 operations access the same register, they are dependent »^ However, only keep dependences to most recentproducer/consumer as other edges are redundant »^ Types of data dependences

Output

Anti

Flow

r1 = r2 + r3r1 = r4 * 6

r1 = r2 + r3r2 = r5 * 6

r1 = r2 + r3r4 = r1 * 6

• 13 -

More Dependences^ Y

Memory dependences

»^ Similar as register, but through memory »^ Memory dependences may be certain or maybe

Y^

Control dependences^ »^

We discussed this earlier » Branch determines whether an operation is executed or not » Operation must execute after/before a branch » Note, control flow (C0) is not a dependence

Mem-output

Mem-anti

Control (C1)

Mem-flow

r2 = load(r1)store (r1, r3)

store (r1, r2)store (r1, r3)

if (r1 != 0)r2 = load(r1)

store (r1, r2)r3 = load(r1)

• 15 -

Dependence Edge Latencies^ Y

Edge latency

= minimum number of cycles necessary

between initiation of the predecessor and successor inorder to satisfy the dependence

Y^

Register flow dependence, a

Æ

b

»^ Latest_write(a) – Earliest_read(b)

Y^

Register anti dependence, a

Æ

b

»^ Latest_read(a) – Earliest_write(b) + 1

Y^

Register output dependence, a

Æ

b

»^ Latest_write(a) – Earliest_write(b) + 1

Y^

Negative latency^ »^

Possible, means successor can start before predecessor » We will only deal with latency >= 0, so MAX any latency with 0

• 16 -

Dependence Edge Latencies (2)^ Y

Memory dependences, a

Æ

b (all types, flow, anti,

output)^ »^

latency = latest_serialization_latency(a) –earliest_serialization_latency(b) + 1 » Prioritized memory operations^ y^

Hardware orders memory ops by order in MultiOp y Latency can be 0 with this support

Y^

Control dependences^ »^

branch

Æ^

b

y^ Op b cannot issue until prior branch completed y^ latency = branch_latency

»^ a

Æ

branch

y^ Op a must be issued before the branch completes y^ latency = 1 – branch_latency (can be negative) y^ conservative, latency = MAX(0, 1-branch_latency)

• 18 -

Dependence Graph Properties - Estart^ Y

Estart = earliest start time, (as soon as possible - ASAP)

»^ Schedule length with infinite resources (dependence height) »^ Estart = 0 if node has no predecessors »^ Estart = MAX(Estart(pred) + latency) for each predecessor node »^ Example

1

2 2 3 3

2

2 4

3

• 19 -

Lstart^ Y

Lstart = latest start time, ALAP

»^ Latest time a node can be scheduled s.t. sched length notincreased beyond infinite resource schedule length »^ Lstart = Estart if node has no successors »^ Lstart = MIN(Lstart(succ) - latency) for each successor node »^ Example

1

2 2

3 3 2

2 4 3