Instruction Scheduling: EPIC Model and Code Sequence Execution, Assignments of Computer Architecture and Organization

Download Instruction Scheduling: EPIC Model and Code Sequence Execution and more Assignments Computer Architecture and Organization in PDF only on Docsity!

Instruction Scheduling

1. This question addresses the EPIC model and its implementation. a. Describe the major differences between EPIC and VLIW approaches to instruction level parallel computing.

EPIC VLIW

Control speculation no control speculation Data speculation no data speculation Predication no predication

Concurrency across instruction Concurrency within a Bundles VLIW word

Static scheduling w/o guarantees Static scheduling with of correctness with hw support code motion only in for correcness the presence of correctness guarantees

2. (a) Consider the following.

a. Convert the following pseudo-code to MIPS style assembly code. Assume the variables are initially in memory. Insert only those load and store instructions that are strictly needed. Label each assembly instruction with numbers from 1 to N, and use the labels to represent the instructions in part b).

a = b + c ; x = a * c ; b = a + c ;

Register alloc: R1 = a, R2 = b, R3 = c, R4 = x

1 LW R2, 0(#b) 2 LW R3, 0(#c) 3 Add R1, R2, R 4 SW R1, 0(#a) 5 Mul R4, R1, R 6 SW R4, 0(#x) 7 Add R2, R1, R 8 SW R2, 0(#b)

b. Draw the dependence graph (as a DAG) for the assembly code you wrote for part a).

3. In the following graph, find all the Hamiltonian cycles. A Hamiltonian cycle is defined as “a path through a graph that starts and ends at the same node and includes every other node exactly once”.

Answer) Hamiltonian Cycles:

a

b c

d

b

a

c

d

a

b c

d

a

b c

d

b) You are to make a schedule for the above instructions. Define the rank of a node as follows:

Rank(x) = max { WL(x,sink), d(x) }

Calculate the rank of each node, and build a sorted list in non-decreasing order of ranks, and apply greedy scheduling on this list. Show your answer by incrementally identifying each successive iteration of greedy list scheduling

Answer) Rank(x) = max { WL(x,sink), d(x) }

We consider two cases for the two weighted path lengths from i1 to i4.

Case i) WL(i1,i4) = 4 (i1->i3->i4)

Rank(i1) = 4 Rank(i2) = 4 Rank(i3) = 2 Rank(i4) = 5

List = <i3,i1,i2,i4> (sorted by non-decreasing ranks) First iteration: <i3,i1,i2,i4>, <i3,i1,i2,i4> i1 selected (first ready insn) ^ ^ Second iteration: <i3,i2,i4> i3,i2 selected. ^ ^

Third iteration: i4 selected. ^ Hence schedule is <i1, _, i3, i2, i4>

Case ii) Consider WL(i1,i4) = 3 (i1->i2->i4)

Rank(i1) = 3 Rank(i2) = 4 Rank(i3) = 2 Rank(i4) = 5 List = <i3,i1,i2,i4> (sorted in non-decreasing order of ranks)

First iteration: <i3,i1,i2,i4>, <i3,i1,i2,i4> i1 is selected. ^ ^

Second iteration: <i3,i2,i4> i3, i2 selected ^ ^ Third iteration: i4 is selected. ^ Final Schedule: <i1, _, i3, i2, i4>.

c) Comment on the optimality of your schedule. Answer) The schedule generated is optimal. Insight: However, the schedule does not meet the deadline criteria for one instruction(i3).

b) Derive a schedule for the above instructions using Greedy List Scheduling. Define and use a rank function. Based on the operation latencies given above, assign latencies to edges/nodes of the dependence graph in any reasonable manner, clearly defining how you have done so. The overall goal is to minimize the number of idle cycles in the final schedule. Show each of the intermediate steps in obtaining your schedule including

• The dependency graph labeled with the latency values
• Initial Rank ordered list of nodes and rank function values
• Intermediate scheduling steps.

All edges have latency 0, except the edge from 3 to 4 which has a latency of 1. This model assumes that each node is assigned a latency of 1. Multiple edges between two nodes are replaced by a single edge.

We will use the Critical Path Length as the rank function. The critical path length of a node is defined as the maximum weighted path from the node to any sink node (ref: HW for the exact expression). Nodes with higher critical path lengths are assigned higher ranks. To calculate weighted path lengths, we also assume that each node has an implicit latency of one cycle. Thus edges emanating from node 3 have a weight of 2-1 = 1.

WL(1) = 3 CPL = 3 WL(2) = 3 CPL = 3 WL(3) = 2 CPL = 2 WL(4) = 0 CPL = 0 WL(5) = 0 CPL = 0

S = {} L = { 1, 2, 3, 4, 5}

S = {1} L = { 2, 3, 4, 5}

S = {1, 2} L = {3, 4, 5}

S = {1, 2, 3} L = {4, 5}

S = {1, 2, 3, 5} L = {4}

Schedule = { 1, 2, 3, 5, 4}

b) Write the code for the hyperblock after if-conversion , i.e., you will have one block of code for the hyperblock and one block of code for basic block L5. For creating a predicate use the following instruction format: pred_le p1, r1, r2 , i.e., if r1<r then p1 is true, else p1 is false. Indicate unambiguously for each predicated instruction in the hyperblock, the value of the predicate that will permit that instruction to complete execution. Your solution should show the correct transfer of control between the code in the hyperblock and the code in basic block L5.

Answer:

(p1 F) means that the instruction will complete execution only if the predicate p1 is false. (p1 T) means that the instruction will complete execution only if the predicate p1 is true.

In the 9 th^ instruction in the hyperblock, if R4 is greater than 0, then control is transferred to the basic block L5.

L1: LD R1, 0(R10) PRED_LE p1, R1, 0 DADD R2, R1, 1 (p1 F) LD R3, 0(R12) (p1 F) LD R4, 0(R6) (p1 F) DADD R4, R4, R2 (p1 F) DADD R4, R4, 1 (p1 T) DADD R2, R2, 1 (p1 T) BGT R4, 0, L DSUB R4, R4, 1 SD 0(R4), R BNE R4, 0, L

L5: DADD R4, R4, 1

SD 0(R4), R

BNE R4, 0, L