Lab Setup - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

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Sequential Logic Design

Lecture

• Agenda

1. FPGA's

2. Lab Setup

• Announcements

1. No Class Monday , Labor Day Holiday

2. HW#2 assigned

Digital Design Flow

• Designing Large Circuits

• this is the ideal process

FPGA's

• What is an FPGA

Field Programmable Gate Array

• An FPGA uses Re-configurable Logic Blocks

• we set the config bits of this block to set its Boolean logic function
• the configuration is a Truth Table (or Look Up Table) of functionality

Out

In

In

config

config Out 000 NOT(In1) 001 NOT(In2) 010 OR 011 NOR 100 AND 101 NAND 110 XOR 111 XNOR

FPGA's

• LUTs = Look Up Tables

• we can program the LUTs to be whatever type of gate is needed by the design
• there are a finite number of LUTs within a given FPGA (also called "resources")

• The LUTs are configured into an ARRAY on the silicon

• Array of LUT's = Array of Gates = Gate Array

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

In1 In2 Out config

FPGA's

• Configuration

• We start with a Gate Level Schematic of our design (from synthesis)
• The FPGA LUTs are configured to implement Gates

LUT LUT LUT

LUT LUT^ LUT

LUT LUT LUT

X

X

X

X

X

X

X

X

X

X

X

X

X X X

X X

FPGA's

• Configuration

• The interconnect switches are then programmed to implement the net connections

LUT LUT LUT

INV OR^ LUT

INV AND LUT

X

X

X

X

X

X

X

X

X

X

X

X

X X X

X X

A

B

C

Out

FPGA's

• Adding More Functionality

• FPGA manufacturer's quickly learned that Flip-Flops would be useful
• They put a DFF next to a 4-Input LUT to form a "Configurable Logic Block" (CLB),
  • CLB also known as Logic Element (LE)

CLB CLB

CLB CLB

X

X

X

X X

FPGA's

• Adding Even More Functionality

• To Improve performance, common logic

functions were "hard coded" on the silicon

• Block RAM
• Adders / Multipliers
• Global Clock Buffers
• even Microprocessors!

Lab Setup

We will use the Altera UP1 FPGA board (found in the CAD Lab)

• PLD Part Numbers
  • Max7128 = EPM7128SLC84-
  • Flex10k = EPF10K20RC240-4 or EPF10K70RC240-
• On-board jumper settings
  • For Max7128 only: Set all 4 jumpers to the UP (TOP) position.
  • For Flex10k20 only: Set the 4 jumpers to DOWN DOWN UP UP position respectively.
  • LEDs, Switches, Seven-Segments
  • VGA, mouse ports
  • 25.175 MHz oscillator
  • EEprom to hold FPGA program
  • 3 expansion ports, each with 42 I/O pins
  • 7 global pins
  • (user's guide on website)

Lab Setup

• Programming the FPGA

• Boundary Scan (JTAG)
  • a daisy chain protocol that allows programming of chips
• FPGA
  • we can program the FPGA direction
  • volatile nature means if we remove power, we'll loose program
• EEprom
  • we can download our code into an on-board EEprom
  • Upon power up, the EEprom will program the FPGA

NOTE: We'll mostly program the FPGA directly

Lab Setup

• Misc

• We will design mainly in VHDL, although Design tools allow schematic entry
• We can design, compile, simulate in either

1) ModelSim

2) Xilinx ISE

3) Altera Quartus II

• We will synthesize, PAR, Verify, and Download in Quartus II

FPGA Overview

• The Real World

• FPGA's historically (mid 90's) have been too expensive for deployment in commercial designs
• ASICs have become very expensive and FPGA's have become more powerful
• As a result, it is now cost effective to use FPGA's in designs
• Learning how an FPGA operates and how to get performance out of them is a

highly sought after engineer skill!