Digital Systems Lab: Latches & Flip-Flops with TTL Families & Temp Ranges - Prof. Janak H., Lab Reports of Electrical and Electronics Engineering

Download Digital Systems Lab: Latches & Flip-Flops with TTL Families & Temp Ranges - Prof. Janak H. and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity!

ECE

DIGITAL SYSTEMS LABORATORY

© Janak H. Patel Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign

Experiment 2

Latches and Flip-Flops

Today’s Topics

z Permissible range of temperature and V CC z TTL Speed and Power Choices z Latches and Flip-Flops z Experiment 2

TTL Families

z Different TTL Families offer a variety of speed andpower consumption options „ 74S Series - Schottky TTL - Higher speed „ 74LS Series - Low Power Schottky TTL „ 74AS Series - Advanced Schottky - faster than 74S „ 74ALS Series - Advanced Low Power Schottky „ 74F Series - Fast TTL - Fast and Low Power z Higher speed normally requires higher power „ Speed-Power Product is a measure of “efficiency” ‹ (propagation delay) x (power consumption per gate) Footnote: A Schottky Transistor is a bipolar transistor that is prevented from reaching saturation byshunting the base and the collector by a Schottky Diode. Schottky diode’s forward voltage drop ismuch less than a standard diode’s, 0.25V vs. 0.6V.

TTL Speed-Power

TTL Family **74S 74LS 74AS 74ALS 74F Maximum Propagation delay (ns) 3 9

4 3 Power per gate (mW) 19 2 8

4 Power-Delay product (pJ) 57 18

12** (Data for a 2-input NAND Gate)

Latches and Flip-flops

z Latches „ Transparent when gating signal is high „ Does not have isolation properties ‹ Cannot build a shift register z Flip-Flops „ Edge Triggered and Master-Slave(Pulse-triggered) „ Both have isolation properties ‹ Can build shift registers, synchronous machines,counters etc. ‹ We will only use Edge-triggered FFs in our designs z Refresh your knowledge from „ ECE 290 Textbook - Mano and Kime „ Additional Notes: “Flip-Flops and Latches” on theECE385 Website

S-R Latch with Gating Signal

S C R Q QN Gate Level Circuit S C R Q Q Symbol S R

Positive-Edge Triggered D-FF

D CLK D C D C Q D CLK Q Q Above Edge Triggered Flip-Flop Captures its D-input on the 0-to-1 Transitionof the CLK and immediately transfers it to the output (Q of latch 2).A Negative Edge Triggered Flip Flop is obtained by inverting the Clock Input QN QN Symbol

Alternative Design

D CLK D C S R Q D CLK Q Q QN QN C^ See Slide 9 Positive-Edge Triggered D-FF

Timing in Edge Triggered FFs

z Set-Up Time „ Minimum time that the input must become stablebefore the edge of the clock z Hold Time „ Minimum time that the input must stay valid afterthe clock edge z Minimum Clock Pulse width z Delay from Clock Edge to Output z Maximum Clock Frequency

Experiment 2

z Before coming to the lab „ Review the data-sheets of ‹ D-FF SN7474, D-latch SN ‹ Edge-Triggered JK-FF SN74LS107A ‹ Negative Edge-Triggered JK-FF SN74LS „ Complete the prelab individually „ With your partner decide on the circuit diagram „ Wire-up the circuit z In the lab „ With enough switches and LEDs observe thebehavior of each of the storage element „ You can correct the waveforms in your prelab afterobserving the correct waveforms