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MIPS Exceptions and Pipelining: Interrupts, Complexity, and Solutions - Prof. Kirk Cameron, Study notes of Computer Architecture and Organization

Virginia Polytechnic Institute and State University (Virginia Tech)Computer Architecture and Organization
Prof. Kirk Cameron

Mips exceptions, focusing on interrupts, pipelining complications, and isa complications. It discusses problem interrupts in each pipeline stage, solutions for simultaneous exceptions, and interrupt complexity in mips and ia-32. The text also covers the influence of multicycle operations on pipelines and solutions like pipelining micro instructions.

Typology: Study notes

Pre 2010

Uploaded on 02/13/2009

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MIPS Exceptions
•Interrupts: 5 instructions executing in 5 stage pipeline
–How to stop the pipeline?
–How to restart the pipeline?
–Who caused the interrupt?
Stage Problem interrupts occurring
IF Page fault on instruction fetch; misaligned memory
access; memory-protection violation
ID Undefined or illegal opcode
EX Arithmetic interrupt
MEM Page fault on data fetch; misaligned memory
access; memory-protection violation
WB None
pf3
pf4
pf5
pf8
pf9
pfa

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MIPS Exceptions

  • Interrupts: 5 instructions executing in 5 stage pipeline
    • How to stop the pipeline?
    • How to restart the pipeline?
    • Who caused the interrupt?

Stage Problem interrupts occurring IF Page fault on instruction fetch; misaligned memory access; memory-protection violation ID Undefined or illegal opcode EX Arithmetic interrupt MEM Page fault on data fetch; misaligned memory access; memory-protection violation WB None

Pipelining Complications

  • Simultaneous exceptions in more than one pipeline stage, e.g.,
    • Load with data page fault in MEM stage
    • Add with instruction page fault in IF stage
    • Add fault will happen BEFORE load fault
  • Solution 1
    • Interrupt ASAP
    • Restart everything that is incomplete
  • Solution 2
    • Precise interrupts – exceptions handled in order they would occur on unpipelined machine - At first interrupt, turn off write control (MEM stage interrupt prevents store) - Post all exceptions to interrupt status vector (one per instr in pipeline) - At WB stage, service any interrupts in order - Guarantees precise interrupts for simple integer pipeline

DADD IF ID EX MEM WB

DADD IF ID EX MEM WB

LD IF ID EX MEM WB

The influence of complexity…

  • Multicycle operations complicate Pipelines
  • Pipelines provide superior throughput
  • Some instructions may take 100s of cycles to complete
  • Fixed number of clock cycles per instruction inefficient
  • Pipelining such instructions too complex
  • Solution: pipeline “micro instructions”
    • Micro instructions are simple building blocks of complex instruction set (CISC in IA-32 or VAX) - Processors of the 1980s
    • Or just start with a reduced instruction set (RISC)
      • Processors of the 1990s
  • Of course multicycle operations like fp are unavoidable and must

be handled as efficiently as possible…

Conceptual view of FP pipeline

  • Suppose FP has same pipeline as INT
  • Two changes
    • EX may be repeated
    • Multiple EX FP units
  • Stalls
    • structural or data hazards
    • EX completion of multi-cycle op
  • Four non-piped functional units
    • int load/store, ALU ops, branches
    • FP and int multiply
    • FP add, sub, conversion
    • FP int, divide

Can’t we pipeline the EX stage further?

Multiple Outstanding Operations

  • Pipelined EX unit allows
    • 4 outstanding FP adds
    • 7 outstanding FP/int multiplies
    • 1 outstanding FP divide

stage names

Requires: Additional temp regs

Multi-cycle Example

RAW hazards

Implementing Hazard Detection and Forwarding

  • Multiple reg writes in single cycle can occur (single write port)
    • Multiple write ports, not efficiently used
    • Track use of write port and stall before issue (ID stage)
  • WAW hazards since WB occur OOO
    • Delay issue of load
    • Stamp out result of add.d
  • Before instruction issue:
    • Check for structural hazards
    • Check for RAW hazards
    • Check for WAW hazards
  • Conceptually the same to implement, yet more cumbersome

Precise Exceptions in Multicycle Ops

DIV F0, F2, F

ADD F10, F10, F

SUB F12, F12, F

  • Assume Add completes prior to divide and SUB causes exception
    • Result: imprecise exception
  • Approaches:
    • Ignore the problem (use imprecise exceptions)
    • Buffer issued ops until earlier ops complete.
      • Expense with large diffs in instruction latency (complex)
    • Allow somewhat imprecise exceptions (utilize software)
    • Allow issue only when you know previous issues will complete before this instruction causes an exception