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ECE 474A/57A
Computer-Aided Logic Design
Lecture 15
Technology Mapping
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Technology Mapping
Previously we performed logic minimization
Minimized size of equation and/or number of literals Didn’t consider how we will implement the circuit
Technology mapping
Transforms technology independent logic network into gates implemented with a technology library standard cell library, gate array library, look-up tables (for FPGAs)
F = w’z’ + wz + yz
F(w, x, y, z) = w’x’y’z’ + w’x’yz + w’x’yz’ + w’xy’z’ + w’xyz + w’xyz’ + wxy’z + wxyz + wx’y’z + wx’yz
F = a + c’
F(a, b, c) = a + a’b’c’ + bc’
F = hi’j’k’ + h’i’ + jk
F(h, i, j, k) = h’i’j’k’ + hi’j’k’ + h’i’k + h’i’j + jk F = w’z’ + wz + yz F = a + c’ F = hi’j’k’ + h’i’ + jk
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Technology Mapping Example
Standard cell ASIC technology
Uses library of pre-layed-out gates or small pieces technology known as cells Designer instantiates and connects these cell to implement a digital circuit
library 1
library 2
F = abcd + a’b’
a b c d a b
F
ab cd
a b
F
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Technology Mapping Phases
Technology mapping broken down into 3 phases
Decomposition
Translate logic network into some primitive cells to create a simple
structure that aids the mapping process
Pattern Matching
Analysis on the circuit library to determine the set of matches for all nodes
in the circuit
Covering
Identify the best possible matches (based on particular cost function) for
logic network so that every node is covered at least once and the
functionality is maintained
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Decomposition
Depending on the input function, circuit may need to be modified
Cell library typically limited to a few primitives functions with few inputs
AND, OR, INV (2-input only)
NAND (2-, 3-, 4-input)
NOR (2-, 3-, 4-input)
Most practical cell libraries limit primitives to 2-input NAND gates and INV
2-input NOR gates work equally
well
Library 1 Library 2
a b
c d
F
c
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Why NAND and NOR Gates?
CMOS Transistor Level Gate Implementation
At the low level NAND/ NOR gates are require fewer transistors than AND/OR
gates and are more desirable to use
a (^) F b
a F b
a F (^) b
a F b
a F
F
0
x
1
NOT gate NOR gate
F
0
1
x y
x y
OR gate
F
0
1
0
1
x y
x y
NAND gate
F
0
1
x y
x y
AND gate
0
1
x y
x y
F
0
1
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Decomposition
Many ways to decompose logic network
Based on delay, size, power, etc.
Typically not limited to 1 decomposition
Multiple versions provided to next step to allow more
opportunity for pattern matching and covering phases
Additional strategy to increase potential pattern
matches – add cascading inverters
Potential to be helpful Make sure leftover cascading inverters covered by wires
Decomposition phase greatly impacts resulting circuit
Tremendous work that considers timing-, layout-, area-
driven decomposition techniques
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Pattern Matching
Several pattern matching techniques available
Combination of matchers frequently used
Structural matcher
Pure structural isomorphic tests
Boolean matcher
Uses BDDs to find matches based on logic
functions
Independent of the actual decomposition
PLA matcher
Similar to Boolean matcher, differs in the
representation of the function
Utilizes truth tables of gates (AND, OR)
1 0
a
d d
c T
E
T E T
E
T
E
f
b b T E ET c E (^) T 1 0
b ET
c T
E
a
c d F
c c
a c
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Pattern Matching
PLA Matcher – AND/OR Truth Table Representation
Programmable logic array (PLA)
Set of programmable AND array linked to programmable OR array
AND Table mimics AND array
Table as wide as number of entries 1 = term positive, 0 = term negative, X = term doesn’t apply
OR Table mimics OR array
Table as wide as number of outputs 1 = term belong to output, 0 = term doesn’t belong to output
F
abc
G
F = abc’ + b’a’
G = ac + a’c’
abc’ b’a’ ac a’c’
AND Table
f g 10 10 01 01
abc 110 00 X 1 X 1 0 X 0
abc’ b’a’ ac a’c’
OR Table
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Covering
After network decomposed and patterns
generated need to select subset of
patterns so entire network is covered
Objective function indicates which subset to choose (delay, cost, reliability, power)
Represent these choices with covering
matrix
Rows represent nodes in graph Column represent pattern matches “1” in matrix signifies node in row covered by pattern in column
How to choose subset of columns?
Find set of columns so all rows covered Choose columns to obtain minimal cost Each match has inputs available from output of other matches
P 1 P 2 … Pn N 1
Nm
N 2
patterns found
nodes in logic
network
Does this look familiar?
Binate covering problem
We already know this is hard to find
exact solution – look at heuristics
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Covering
Dynamic Programming
Propose mapping method based on tree- covering
Network partitioned into forest of trees
Solve problem by solving for each tree
Stitch trees back together
Motivated by existence of efficient dynamic
programming algorithm available
General idea of dynamic programming
Optimal substructure
Overlapping sub-problems
Memoization
optimal solutions of sub-problems can be used to find the optimal solutions of the overall problem
same sub-problems are used to solve many different larger problems.
savings and re-use of already-computed sub-solutions
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Example 3
Dynamic Programming
Cover following circuit using dynamic programming approach cell library
INV (1)
numbers in parenthesis represent cost
b
NAND2 [a] (2)* NAND2 (2)
NAND3 (3)
AOI21 (3)
a
d
g
c
e f
j
i
h Start with leaves to root Given node, look for best cover of subtree based on node
Node a NAND2 is only match, cost of 2 *** indicates best solution for subtree** [] indicates which nodes are covered by pattern
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Example 3
Dynamic Programming
Cover following circuit using dynamic programming approach
cell library
INV (1)
numbers in parenthesis represent cost
b
NAND2 [a] (2)* NAND2 (2)
NAND3 (3)
AOI21 (3)
a
d
g
c e f
j
i
h
NAND2 [i] (5) NAND3 [i, h, g] (3)*
INV [b] (1)*
INV [d] (1)*
NAND2 [g] (2)* (^) INV [h] (3)*
NAND2 [c] (5)*
NAND2 [e] (8) INV [f] (9) AOI21 [f, e, c, d] (6)**
Node h INV is only match, cost of 3 (2 + 1)
Node i NAND2 is a possible match, cost is 5 NAND3 is a possible match, cost is 3
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Example 3
Dynamic Programming
Cover following circuit using dynamic programming approach cell library
INV (1)
numbers in parenthesis represent cost
b
NAND2 [a] (2)* NAND2 (2)
NAND3 (3)
AOI21 (3)
a
d
g
c
e f
j
i
h
NAND2 [i] (5) NAND3 [i, h, g] (3)*
INV [b] (1)*
INV [d] (1)*
NAND2 [g] (2)* (^) INV [h] (3)*
NAND2 [c] (5) NAND2 [e] (8) INV [f] (9) AOI21 [f, e, c, d] (6)*
NAND2 [j] (11) NAND3 [j, f, e] (12)*
Node j NAND2 is a possible match, cost is 11 NAND3 is a possible match, cost is 12
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Example 3
Dynamic Programming
Cover following circuit using dynamic programming approach cell library
INV (1)
numbers in parenthesis represent cost
b
NAND2 [a] (2)* NAND2 (2)
NAND3 (3)
AOI21 (3)
a
d
g
c
e f
j
i
h
NAND2 [i] (5) NAND3 [i, h, g] (3)*
INV [b] (1)*
INV [d] (1)*
NAND2 [g] (2) INV [h] (3)**
NAND2 [c] (5) NAND2 [e] (8) INV [f] (9) AOI21 [f, e, c, d] (6)*
NAND2 [j] (11) NAND3 [j, f, e] (12)*
Now we backtrack starting from root and choose the best covering seen
At node j, NAND2 gives best cost
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Example 3
Dynamic Programming
Cover following circuit using dynamic programming approach
cell library
INV (1)
numbers in parenthesis represent cost
b
NAND2 [a] (2)* NAND2 (2)
NAND3 (3)
AOI21 (3)
a
d
g
c e f
j
i
h
NAND2 [i] (5) NAND3 [i, h, g] (3)*
INV [b] (1)*
INV [d] (1)*
NAND2 [g] (2)* (^) INV [h] (3)*
NAND2 [c] (5)*
NAND2 [e] (8) INV [f] (9) AOI21 [f, e, c, d] (6)**
NAND2 [j] (11) NAND3 [j, f, e] (12)*
At node f, AOI21 gives best cost At node a, NAND2 gives best cost At node b, INV gives best cost At node i, NAND3 gives best cost
FINAL COST = 11
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Conclusion
Technology mapping phases
Decomposition
Pattern Matching
Covering
Only considered a few techniques
Many more exist with alternative constraints
Delay, Power, Reliability, Layout, Congestion, etc.
Others look at two phase technology mapping
Simplify technology mapping by finding a minimal area solution Apply post technology mapping transformations to customize solution to specific interest
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ECE 474A/57A
Computer-Aided Logic Design
Lecture 16
Course Summary and Additional Topics
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Pipelining
W1 D1 W2 D2 W3D
Without pipelining:
With pipelining:
“Stage 1”
“Stage 2”
Time
W
D
W
D
W
D
a
Intuitive example: Washing dishes with a
friend, you wash, friend dries
You wash plate 1
Then friend dries plate 1,while you wash
plate 2
Then friend dries plate 2, while you wash plate 3; and so on You don’t sit and watch friend dry; you start on the next plate
Pipelining: Break task into stages, each
stage outputs data for next stage, all stages
operate concurrently (if they have data)
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Concurrency
Concurrency : Divide task into subparts,
execute subparts simultaneously
Dishwashing example: Divide stack into 3 substacks, give substacks to 3 neighbors, who work simultaneously -- 3 times speedup (ignoring time to move dishes to neighbors' homes) Concurrency does things side-by-side; pipelining instead uses stages (like a factory line)
Task
Concurrency Pipelining
Can do both, too
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ECE 474a/575a Susan Lysecky
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Component Level Optimization and Tradeoffs
delay
carry-select
carry-
ripple
carry-lookahead
multilevel
carry-lookahead
size
Designer picks the adder that satisfies
particular delay and size requirements
May use different adder types in different parts of same design Faster adders on critical path, smaller adders on non-critical path
FA
a
co s
b
FA
a0b0 ci
FA
a
s2 s1 s
b
FA
a1b 4-bitCLA logic
4-bitCLA logic
4-bitCLA logic
4-bitCLA logic
4-bitCLA logic
4-bitCLA logic
4-bitCLA logic
4-bitCLA logic 2-bitCLA logic
4-bitCLA logic
4-bitCLA logic
P G c SPG block
P
P P
GP^ P^ P^ P^ P^ P^ P
G G
cG^ G^ G^ G^ G^ G^ G
c c
c c c c c c c
carry-ripple adder carry-lookahead adder
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Power Optimization
Until now, we’ve focused on size and delay
Power is another important design criteria
Measured in Watts (energy/second) Rate at which energy is consumed
Increasingly important as more transistors fit on a chip
Power not scaling down at same rate as size Means more heat per unit area – cooling is difficult Coupled with battery’s not improving at same rate Means battery can’t supply chip’s power for as long CMOS technology: Switching a wire from 0 to 1 consumes
power (known as dynamic power )
P = k * CV^2 f k: constant; C: capacitance of wires; V: voltage; f: switching frequency Power reduction methods Reduce voltage: But slower, and there’s a limit What else?
energy (1=value in 2001)
(^8)
4
2 1
battery energy density
energy demand
2001 03 05 07 09
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Power Optimization using Clock Gating
P = k * CV^2 f
Much of a chip’s switchingf (>30%) due to
clock signals
After all, clock goes to every register Portion of FIR filter shown on right Notice clock signals n1, n2, n3, n
Solution: Disable clock switching to registers
unused in a particular state
Achieve using AND gates FSM only sets 2nd^ input to AND gate to 1 in those states during which register gets loaded
Note: Advanced method, usually done by
tools, not designers
Putting gates on clock wires creates
variations in clock signal ( clock skew); must
be done with great care
yreg
xt0 c0 xt1 c1 xt2 c X
x_ld
y_ld
clk n1 n2 n3 n
yreg
X xt0^ c0 xt1^ c1 xt2 c
x_ld
y_ld
n2 n3 n
n clk
clk n1, n2, n n
Much switching on clock wires
clk n1, n2, n n
Greatly reduced switching – less power
s
s
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Power Optimization
Low-Power Gates on Non-Critical Paths
Another method: Use low-power gates
Multiple versions of gates may exist Fast/high-power, and slow/low-power, versions Use slow/low-power gates on non-critical paths Reduces power, without increasing delay
g
f
e
d
c
a b
F
26 transistors 3 ns delay 5 nanowatts power
nanowatts nanoseconds (^) gf
e
d
c
a b
F
26 transistors 3 ns delay 4 nanowatts power
low-power gates delay
high-power gates low-power gates on non-critical path
size
Digital Design Copyright © 2006 Frank Vahid
