ECE 2030 Exam I - Electrical Engineering Problem Set, Exams of Computer Science

The instructions and problems for exam i of ece 2030, a course in electrical engineering at georgia tech. The exam consists of 5 questions, including filling in tables, constructing truth tables, and designing switch level implementations. Assumptions and clarifications are required for some problems, and partial credit may be given with written solutions.

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2012/2013

Uploaded on 04/08/2013

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ECE 2030
Section E
Exam I
September, 22nd
1. The Georgia Tech Honor Code governs this examination.
2. There are 5 questions and 8 pages including two blank worksheets. Make sure you
have all of them.
3. Please write/draw legibly. Use the work sheets for generating the solutions before
providing the final answer.
4. State any assumptions you feel you have to make or ask for clarification
5. Keep in mind it is difficult to give partial credit without written material. Please
make sure you document any partial solutions.
6. Plan your work!
Problem Max Points Graded
1
2
3
4
5
Total 100
Student Name: __________________________________
Student Number: ________________________________
pf3
pf4
pf5

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ECE 2030

Section E

Exam I

September, 22nd

  1. The Georgia Tech Honor Code governs this examination.
  2. There are 5 questions and 8 pages including two blank worksheets. Make sure you have all of them.
  3. Please write/draw legibly. Use the work sheets for generating the solutions before providing the final answer.
  4. State any assumptions you feel you have to make or ask for clarification
  5. Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 6. Plan your work!

Problem Max Points Graded 1 2 3 4 5 Total 100

Student Name: __________________________________

Student Number: ________________________________

1.a) Fill in the following table Binary Decimal 10110 42 11101

b) Fill in the following table Gate # Transistors 3 input NOR gate Inverter 3 input AND gate

c) Fill in the following table Standard Gate DeMorgan’s Equivalent Gate

  1. Construct a switch level implementation of the following Boolean expression.

F = AB + BC + AC

  1. Using a mixed logic design strategy provide an implementation of the following Boolean expression using only 2 input NOR gates. How many transistors does this implementation have? Do NOT simplify this expression.

F=ABCD + AB