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This is a closed book, closed note exam for ece 2030 computer engineering course in spring 2001. It consists of 4 problems, covering topics such as number systems, digital logic design, and multiple choice questions related to 32-bit representations.
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4 problems, 5 pages Exam Two 21 March 2001
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 5 pages Exam Two 21 March 2001
Problem 1 (3 parts, 30 points) Numbers and Arithmetic
Part A (9 points) Convert some binary values (and powers of two) into decimal notation:
binary notation decimal notation
11101100
225
Part B (9 points) Convert the following octal values into hexadecimal notation:
octal notation hexadecimal notation
77
3546
Part C (12 points) For each problem below, (a) compute the operations using the rules of addition, (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.
addition result signed error? unsigned error?
4 problems, 5 pages Exam Two 21 March 2001
Problem 3 (3 parts, 30 points) Counters
Part A (10 points) Design a toggle cell using transparent latches, 2-input XOR gates, and 2-input basic gates (AND, OR, NAND, NOR, and NOT). Include a toggle enable TE, active low clear CLR, and a two-phase non-overlapping clock PHI1 and PHI2. Label the output OUT.
Part B (10 points) Now use copies your toggle cells (in icon form) to build a divide by four counter. This design should include an active high external count enable CE and an active high external clear CLR. You do not need to draw in the clock signals. Assume all toggle cells are connected to the two-phase clock. Label all of your outputs signals.
4 problems, 5 pages Exam Two 21 March 2001
Part C (10 points) Now use copies of your toggle cell (in icon form) to build a divide by five counter. This design should include an active high external count enable CE and an active high external clear CLR. Your design should clear if (A) the external clear CLR is high, or (B) the maximum output count is reached and the count enable is high. You do not need to draw in the clock signals.
Problem 4 (4 parts, 12 points) Multiple Choice
Consider four different 32-bit representations: (A) an unsigned integer representation, (B) a twos complement integer representation, (C) a twos complement fixed point representation with sixteen bits on each side of the fixed point, and (D) a floating-point representation with a 23 bit mantissa and an 8 bit exponent. For each quantity below, circle which representation (A, B, C, or D) most accurately represents the quantity (i.e., which representation can represent the value with the smallest error).
