Logic Building Blocks - Introduction to Computer Engineering | ECE 2030, Study notes of Electrical and Electronics Engineering

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INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

•CHAPTER VI

CHAPTER VI

COMBINATIONAL LOGIC BUILDING BLOCKS

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

COMBINAT. LOGIC

INTRODUCTION

- COMBINATIONAL LOGIC-INTRODUCTION -^ Combinational logic•

Output at any time is determined completely by the current input.

-^ We will later consider circuits where the output is determined by theinput and the current state (memory) of the system. -^ In this chapter we will consider some useful building blocks that can bepieced together and used in larger designs. This will include: -^ Multiplexers (selectors) and demultiplexers (distributors)•^ Encoders, priority encoders, decoders•^ Adders (full and half)•^ Parity generators and parity checkers•^ Shifters and rotators•^ Comparators

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

DECODERS

DECODERS WITH ENABLE

- COMBINATIONAL LOGIC • DECODERS-BASIC DECODER -^ Often, combinational logic building blocks will also have an enable line thatturns on outputs or leaves them off.

3-to-

Decoder

A^0 A^1 A^2

D^0 D^1 D^2 D^3 D^4 D^5 D^6 D^7

3-to-8 Decoderwith Enable

Module Enable

E

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

DECODERS^ TRUTH TABLES

- COMBINATIONAL LOGIC • DECODERS-BASIC DECODER-WITH ENABLE -^ Truth table for a

3-to-8-line decoder

D^2

D^3

D^4

D^1

D^0

D^5

D^6

D^7

Outputs

Inputs

A^0

A^1

A^2

E 1 1 1 1 1 1 1 1

X^

X^

X^

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

DECODERS

DESIGNING WITH DECODERS

- DECODERS-WITH ENABLE-TRUTH TABLES-IMPLEMENTATION -^ Any Boolean function can implemented using a

decoder

and

OR

gates by

ORing together the function

’s^ minterms

F^2

Outputs F^1

Inputs

A^0

A^1

A^2

3-to-

Decoder

A^0 A^1 A^2

F^1 F^2

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

DECODERS

DECODER NETWORKS

- DECODERS-TRUTH TABLES-IMPLEMENTATION-DESIGNING W/DECODERS -^ We can also use multiple decoders to form a larger decoder.

2-to-

Decoder

A^0 A^1

D^0 D^1 D^2 D^3 D^4 D^5 D^6 D^7

E

2-to-

Decoder

A^2

E

3-to-8 Decoder Implementedwith two 2-to-4 Decoders

A^2

used with enable input to control which decoderwill output the

^1.

A^1

and

A^0

used to select

which output on specificdecoder will output

^1.

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

ENCODERS

ENCODER TRUTH TABLE

- DECODERS • ENCODERS-BASIC ENCODER -^ Truth table for an

8-to-3-line encoder

-^ Assumed that only one input is

^1. What happens if more then one is

^1?

D^2

D^3

D^4

D^1

D^0

D^5

D^6

D^7

Outputs

Inputs

A^0

A^1

A^2

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

ENCODERS

DESIGNING WITH ENCODERS

- DECODERS • ENCODERS-BASIC ENCODER-TRUTH TABLE -^ Encoders are useful when the occurrence of one of several disjoint eventsneeds to be represented by an integer identifying the event.

8-to-

Encoder

0 1 2 3 4 5 6 7

N^

NE

E

SE

S

NW W SW

Example: Wind direction encoder

1 E

pp. 253-254 of Ercegovac, Lang and Moreno,

“Introduction to Digital Systems

”, 1999.

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

ENCODERS

DESIGN WITH P-ENCODER

- ENCODERS-TRUTH TABLE-DESIGN W/ ENCODERS-PRIORITY ENCODERS -^ Priority encoders are useful when inputs have a predefined priority and wewish to select the input with the highest priority.

2-to-

Priority 0 1 2 3

(^0212) Encoder

Device ADevice BDevice CDevice D

LowestPriority HighestPriority RequestLines

Processor

1 E Ac

Example: Resolving interrupt requests

pp. 253-256 of Ercegovac, Lang and Moreno,

“Introduction to Digital Systems

”, 1999.

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

MULTIPLEXERS

BASIC MULTIPLEXER (MUX)

- ENCODERS-DESIGN W/ ENCODERS-PRIORITY ENCODERS-DESIGN W/ P-ENCODERS -^ Selects one of many inputs to be directed to an output.

4x

Multiplexer S^1

S^0

f

X^

Y

A^0 A^1 A^2 A^3

0 X 1 X

X X X X

X^0 X^1

X X X X

A^0

=^0

A^2

=^0

A^0

=^1

A^2

=^1

A^2

A^3

Y^

A^1

A

0

X

Output

Inputs

F

X X X X

0 X 1 X

X X X X

X^0 X^1

A^1

=^0

A^3

=^0

A^1

=^1

A^3

=^1

E

Module Enable

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

MULTIPLEXERS

DESIGN WITH MULTIPLEXERS

- ENCODERS • MULTIPLEXERS-BASIC MULTIPLEXER-USING PASS GATES -^ Any Boolean function can be implemented by setting the inputscorresponding to the function and the selectors as the variables.

F^1

Z

Y

X

8x

Multiplexer S^2

S^1

f

X^

Y

E

Module Enable

S^0 Z

Example:

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

DEMULTIPLEXERS^ BASIC DEMULTIPLEXER

- MULTIPLEXERS-BASIC MULTIPLEXER-USING PASS GATES-DESIGN W/ MULTIPLEX. -^ Takes one input and selects one of many outputs to direct the input.

1x

Demultiplexer

W

D^0 D^1 D^2 D^3

W=

W=

0 W=^00 W=^1

D^2

D^3

Y^

D^1

D

0

X

Outputs

Inputs

W

W=

W=

0 W=^00 W=^1

E

Module Enable

S^1

S^0 X Y

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

SHIFTERS BASIC SHIFTER

- MULTIPLEXERS • DEMULTIPLEXERS-BASIC DEMULTIPLEXER-DESIGN W/ DEMULTIPLEX -^ A shifter takes a set of inputs and shifts it to the right or left.

4-bitShifter

D^0

D^1

D^2

D^3

E^

Module Enable

A^0

A^1

A^2

A^3

L/R

s^ d

Y/N

Shift (Yes/No)Direction(Left/Right)

INTRO. TO COMP. ENG. R.M. Dansereau; v.1.

CHAPTER VI-

SHIFTERS

COMMON SHIFTERS

- MULTIPLEXERS • DEMULTIPLEXERS • SHIFTERS-BASIC SHIFTERS -^ A whole variety of other shifters are possible such as

4-bitShifter

D^0

D^1

D^2

D^3

E

A^0

A^1

A^2

A^3

L/R

s^ d

Y/N Ins q

Value toinsert intoempty spot

4-bitShifter

D^0

D^1

D^2

D^3

E

A^0

A^1

A^2

A^3

L/R

d s 0 Distance (in binary)

distance of how far to shift s^1

Ddisc Value discarded

from shift