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ECE 4100/6100 Fall 2006
ECE 4100/6100: Assignment 3 ñ Coherent Caches
This assignment is to be performed individually. You may engage in general discussions about methodology, tool specifics, behaviors one can expect to see, relationships between machine parameters and application parameters, etc., but the assignment must be done individually. Any clarifications of goals of the assignment should be addressed to the TA and Prof. Yalamanchili.
The project will use memory reference traces provided to you. They are uniprocessor.dat and multiprocessor.dat.
Due date: November 20
th
, 6pm via email.
Submission Instructions: Mail your report to the TA ([email protected]). Follow all submission guidelines as posted on the class site.
Part I: Cache Simulator
Develop a simulation model for a set-associative, true LRU replacement, write-back, unified L cache that is parameterized by line size, associativity, and cache size. Test this implementation by recording the miss rate for 8 Kbyte, set associative cache as a function of associativity (2, 4,
- and line size (16, 32 and 64 bytes) for uniprocessor.dat.
Part II: Cache Coherency
Update your cache controller logic to support the three-state (MSI) snooping cache coherence protocol described in the text. Execute this simulation with the trace file multiprocessor.dat. Run experiments for a 16 Kbyte, and plot the number of invalidations as a function of line size and associativity for the same ranges as Part I. Explain the observed behavior.
Figure 1 : System Architecture for Part II. Your program must simulate a cache controller within this system as highlighted.
Processor 0 Execution Core
Processor 0 Cache Controller
Processor 1 Processor 2
Processor n
Processor 0 Cache
Local Traffic
Remote Traffic
Your Simulator
ECE 4100/6100 Fall 2006
Trace File Format: Dinero trace files are all ASCII (meaning you will need to convert strings to integers). Each line contains three data fields: a source code, a type-of-access code, and a hexadecimal address (without a preceding ë0xí). The source code indicates the source of the memory operation ñ ë1í for the local and ë2í for a remote processor coming over the bus (in Part I, you can simply drop remote operations). The type-of-access code specifies the type of memory operation (see the example for specific code meanings). A NOP (meaning no memory operations occur this cycle) is specified by the ë0 0 0í pattern. Optionally, comments may be included after the address. All fields ñ source code, access code, address, and comment ñ are space-delimited. The address space is 32 bits. Instruction fetches are word-aligned, but data accesses may address any byte. Below is an example
1 2 20c Comment 1 2 210 Another comment 2 0 1fc780 ‘0’ means read data 2 1 7fffcca6 ‘1’ means write data 0 0 0 1 3 54 2 4 531e0 ‘3’ and ‘4’ are invalid accesses that cause a cache flush 2 2 218 ‘2’ means instruction fetch 1 2 21c 0 0 0
Your final report is limited to 4 pages, using a 12 point times roman font and one inch margins on all sides. The report must be submitted in PDF[2]^. The format of the report is as follows:
- Title and Author
- Abstract (summarize the reports conclusions in 100 words or less)
- Explanation of observed trends. Summarize critical results, key insights learned about the effect of the various architectural parameters examined on performance, and how this assignment could have been improved (e.g., to provide other insights that you indirectly discovered).
Additionally, the final version of your source code (with the three-state coherence protocol) must be submitted separately, along with script and README files. The script file needs to compile and execute your source code on the CoC 309 Linux machines. The README file must explain how to change the trace file your program takes as input (the simpler this change, the better).
Be sure to allow adequate time to run the simulations, analyze the results, and write a thorough, readable report. Your grade on this project will be based primarily on your presentation and analysis of the data. Try to summarize data in a clear manner using tables and/or graphs. Every table or graph you include must be referenced somewhere in your discussion. Conciseness and precision is valued over volume.
[1] Assume for this lab that a word is 32 bits [2] Open Office, available on the lab machines, will export directly to PDF. For Word documents, go to Adobeís website and create an account, which will allow you five free conversions.
