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PSW-process status word
R
R
R
R
PC, program counter
IR, instruction register
MAR
MDR
ALU
Address Bus
Data Bus Control Bus
System Bus Memory
CPU/Processor
(+,-,*, etc)
Add R1,R2,R
Control Unit
Register File
Load R2, X
Load R3, Y
Store R1, SUM
Program Area
(X) (Y) (SUM)
5 3 0
DataGlobal
Heap
Stack
Unused
Operating System Area
0 1 2 3..
.
.
.
.
(Addresses)
A Program's Address Space
Disk
I/O Controller
Instruction/Machine Cycle of stored-program computer - repeat all day
- Fetch Instruction - read instruction pointed at by the program counter (PC) from memory into Instr. Reg. (IR)
- Decode Instruction - figure out what kind of instruction was read
- Fetch Operands - get operand values from the memory or registers
- Execute Instruction - do some operation with the operands to get some result
- Write Result - put the result into a register or in a memory location
Note: Sometime during the above steps, the PC is updated to point to the next instruction.
Lecture 3 - 1
Serial Execution - complete fetch-decode-execute cycle before starting the next instruction
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 1
time
Instruction Pipelining - assembly-line idea used to speed instruction completion rate
Assume that an automobile assembly process takes 4 hours.
Chassis Motor Interior Exterior
If you divide the process into four equal stages, then ideally
time between completions =
time to complete one car
of stages
Problems: stages might not be balanced overhead of moving cars between stages two stages need same specialized tool (structural hazard)
Pipelined Execution - goal is to complete one instruction per clock cycle
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 1
time
Lecture 3 - 2
Data Hazards - the problem
SUB R4, R3, R5 FI DI CO FO EI WO
ADD R3, R2, R1 FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
Solution Alternatives:
- Introduce stalls
SUB R4, R3, R5 FI DI CO stall stall FO EI WO
ADD R3, R2, R1 FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
- Add additional hardware ( bypass-signal paths ) to “ foward ” R3’s new value to the SUB instruction:
FI/DI
latch
DI/CO
latch
CO/FO
latch
FO/EI
latch
EI/WO
latch
FI DI CO^ FO^ EI^ WO
Decoder
ALU
ALU
ALU
Data (^) Data Memory (^) Memory
Register
Register
Register File
File
File
Instr. Memory
Copy of Instr.
Decoded CO-ALU do +
Opcode operand 1 addr. operand 2 addr (or reg#)
old value of R
value of R
SUB
dest. addr/reg
dest. reg R
R3 result value
EI-ALU do *
M
M
U
U
X
X
ADD
a bypass-signal path
No stalls needed in this case.
SUB R4, R3, R5 FI DI CO FO EI WO
ADD R3, R2, R1 FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
What would control the MUX?
Lecture 3 - 4
MUX Operation:
Inputs^ Output
Control Signals - (binary #) to select which input gets sent to output
Consider the following code: ADD R3, R2, R LOAD R4, 4(R3)
What would the timing be without bypass-signal paths/forwarding?
LOAD R4, 4(R3) FI
ADD R3, R2, R1 FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
This assumes that R3 cannot be written and the new value read in the same stage.
If we assume that R3 can be written in the first half of the WO stage and its new value read in the last half of the DI stage, then we get:
LOAD R4, 4(R3) FI
ADD R3, R2, R1 FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
What would the timing be with bypass-signal paths?
Lecture 3 - 5
Consider a larger section of code. What would the timing be without bypass-signal paths/forwarding (use “stalls” to
solve the data hazard)? (This code might require more or less that 15 cycles)
ADD R5, R3, R
SUB R6, R1, R
LOAD R1, 4(R3)
STORE R3, 8(R4)
ADD R3, R2, R1 FI
LOAD R4, 16(R3) FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
(Assume that a register cannot be written and the new value read in the same stage.)
b. What would the timing be with bypass-signal paths?
(This code might require more that 15 cycles)
ADD R5, R3, R
SUB R6, R1, R
LOAD R1, 4(R3)
STORE R3, 8(R4)
ADD R3, R2, R1 FI
LOAD R4, 16(R3) FI DI CO FO EI WO
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Time d
(Assume that a register cannot be written and the new value read in the same stage.)
c. Draw ALL the bypass-signal paths needed for the above example.
FI/DI
latch
DI/CO
latch
CO/FO
latch
FO/EI
latch
EI/WO
latch
FI DI CO FO EI WO
Decoder
ALU
ALU
ALU
Data (^) Data Memory (^) Memory
Register
Register
Register File
File
File
Instr. Memory
Copy of Instr.
Decoded CO-ALU do +
Opcode operand 1 addr. operand 2 addr (or reg#)
operand 1 value
operand 2 value
opcode
dest. addr/reg
dest addr/reg
result value
EI-ALU do *
Lecture 3 - 7
