Download Memory - Digital Circuits and Systems - Lecture Notes and more Study notes Computer Science in PDF only on Docsity!
Digital Circuits and Systems
Section 1 - Combinatorial Logic
1.1 Encoders:
Definition
- An encoder produces a digital code which depends on which one of its input is activated
- Only one of M inputs is activated at a time
- Encoder outputs a N-bit output code
- Always: 2N^ ≥ M
Example
I 0 Enc
I 1
I 2
O 0
O 1
ON-
I M
- 4-Line to Binary Encoder:
o 4 inputs o 2 outputs
- The logic diagram can be generated using formal methods:
Y = D + C
X = D + B
Y
AB/CD 00 01 11 10
00 X 1 X 1
01 0 X X X
11 X X X X
10 0 X X X
Inputs Outputs A B C D Y X 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1
A Enc
B
C
Y
X
D
1.2 Decoders:
Definition
- An decoder activates only one of its outputs depending on the binary code provided as input
- Decoder receives a N-bit input code
- Only one of M outputs is activated at a time
- Always: 2N^ ≥ M
I N-
Dec O^0
O 1
O 2
OM-
I 0
I 1
Example
- Binary to 4-Line Decoder:
o 2 inputs o 4 outputs
- The logic diagram can be generated using formal methods:
_ _ _ _
A = X Y, B = X Y, C = X Y, D = X Y
A
X/Y 0 1
Inputs Outputs X Y A B C D 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1
Dec A
B
C
X
Y
D
4 1 2 3
3 1 2 3
2 1 2 3
1 0 1 2 3
0 0 1 2 3
S
S
S
S
S B B B B
9 0 3
8 0 3
7 1 2 3
6 1 2 3
5 1 2 3
S B B
S B B
S B B B
S B B B
S B B B
S 0
B 0 B 1 /B 2 B 3 00 01 11 10
11 X X X X
10 0 0 X X
Inputs Outputs B 0 B 1 B 2 B 3 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1
• Implementation
- Horizontal segments: a, c, f
a => 0, 2, 3, 5, 6, 7, 8, 9 c => 2, 3, 4, 5, 6, 8, 9 f => 0, 2, 3, 5, 6, 8, 9
a
AB/CD 00 01 11 10
11 X X X X
10 1 1 X X
a = A + C + BD + B D
c
AB/CD 00 01 11 10
11 X X X X
10 1 1 X X
c = A + BC + CD + B C
f
AB/CD 00 01 11 10
11 X X X X
10 1 1 X X
What’s missing?
f = A + BCD + CD + BC + B D
- Implementation (a segment)
A
B
B
C
D
a
1.3 Multiplexers:
Definition
- A multiplexer selects one of its inputs to direct to the output depending on the binary code provided at the select inputs
- Multiplexer receives a M-bit selection code
- Only one of N inputs is directed at the output
- Always: 2M^ = N
I N-
Mux
Z
I 0
I 1
S 0 S 1 SM
Example 1
o 2 inputs o 1 select input o 1 output
- The logic diagram can be generated using formal methods and minimising, it results:
_
Z = A S + B S
Inputs Select Output A B S Z 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1
S
S
Mux
Z
A
B
- Homework: implementation using gates!
Example 3
- Four-channel Multiplexer o 4 inputs o 2 select input o 1 output
- We have:
_ _ _ _
Z = I 0 S 1 S 0 + I 1 S 1 S 0 + I 2 S 1 S 0 + I 3 S 1 S 0
S 1 S 0 Z 1
0 0 I 0
0 1 I 1
1 0 I 2
1 1 I 3
____^ I^0 ____S^1 S 0 ____^ I^1 S 1 S 0 I 2 ____S^1 S 0 I 3 S 1 S 0
Z 0
Z
I 1 Mux
I 2
I 0
I 3
S 0 S 1
- Homework: implementation with 2-channel MUX
Example 4
- Eight-channel Multiplexer o 8 inputs o 3 select input o 1 output
- We have:
_ _ _ _ _
Z = I 0 S 2 S 1 S 0 + I 1 S 2 S 1 S 0 + … + I 7 S 2 S 1
S 0
- Homework: implementation with 2-channel MUX
- Homework: implementation with logic gates
Applications
S 2 S 1 S 0 Z 1
0 0 0 I 0
0 0 1 I 1
0 1 0 I 2
0 1 1 I 3
1 0 0 I 4
1 0 1 I 5
1 1 0 I 6
1 1 1 I 7
S 0 S 1
Z
I 1 Mux
I 6
I 0
I 7
S 2
Application 1
- Parallel to serial conversion:
o 4 inputs o 1 output o 4-bit Register o 2-bit Counter o 4-channel Mux o 1 serial line
- The Register contains parallel data
- 2-bit Counter generates S1 and S
Serial
line
X 0
X 1
X 2
X 3
2-bit
Counter
4:1 line MUX
S1 S
Clock
- At every Clock, a different input of the 4:1 line
Mux is outputted on the Serial line: X0, X1, X2,
X 3
