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Memory Organization and Addressing
Memory is based on binary bits. Each bit can hold one of two values: 0 or 1. Except for unusual designs, individual bits in memory are not directly addressable by the CPU (Central Processing Unit). The old IBM 1401 could access bits directly. The most common memory groupings are as follows: 8 bits a byte 16 bits a word (some call this a short word) 32 bits a longword (some call this a word) The term “word” is somewhat ambiguous due to multiple definitions. In this course, we refer to “16–bit word”, “32–bit word”, etc. In some computers, a word is the smallest addressable memory unit. Most of these, such as the CDC–6600 (60–bit words) are now obsolete. In a byte–addressable computer (such as the Intel Pentium series), each byte is addressable individually, although 32–bit words can be directly accessed. All computers with byte addressing provide instructions to access both 16–bit words and 32–bit longwords. The CPU just accesses two or four bytes at a time.
Memory Organization and Addressing (Part 2)
Memory is often described by a notation with the structure (L x W) L is the number of addressable units in memory W is the number of bits in memory The old CDC–6600 usually had a 256 K x 60 memory. This was 256 1024 = 262, 144 words, each of 60 bits. Yes, this was called a “supercomputer”. A modern Pentium might have a memory described as 512 M x 8; 512 2 20 = 512 1, 048, 576 = 536,870,912 addressable units, each with 8 bits. This would be called a 512 MB memory. Main memory sizes are not quoted in bits. Memory chip sizes often are quoted in bits, but could be quoted in numbers of 4–bit elements as well as 8–bit bytes. Common notation: 1K = 2 10 = 1, 024 (almost never seen these days) 1M = 2 20 = 1, 048, 576 1G = 2 30 = 1, 073, 741, 824
Views of Primary Memory
We may view Primary Memory either in its logical view or pay attention to reality. The logical view of memory treats it as a very large addressable array. Addresses go into the MAR and data travels through the MBR. It might be declared as byte : memory [266 435 456] This view is good logically, but impossible to construct. Consider the 28–to–266, 435, 456 decoder we have just ordered up.
Memory as a Collection of Chips
In fact, physical memory is built from standard memory chips. For example, a 256 MB memory might be built from sixteen 16 MB chips, each of which might itself be implemented as eight 16 Mb (megabit) chips; a total of 128 chips. Consider the textbook’s example: a 32 KB memory built from 4KB chips. 32 KB = 2 15 bytes and 4 KB = 2 12 bytes. We need ( 15 / 2 12 ) = 2 3 = 8 chips. In standard fashion, these chips will be numbered as 0 through 7 inclusive. We need a 15–bit address for this memory. Address bits are numbered 14 through 0. Here we adopt low order interleaving. Consecutive addresses are placed in different chips. This facilitates faster access to memory. Here is the textbooks figure showing the location of the first 32 addressable bytes.
Why have low–order interleaving?
This choice is due to the principle of locality; memory locations tend to be accessed one after another. If consecutive locations are in different chips, the CPU can initiate a number of memory–read operations at a rate faster than the memory chips can handle. Consider the organization from the book, with an 8–way low interleaving. Suppose that the CPU wants to fill a cache line with the eight bytes, indexed 8 to 15. The CPU sends an address and READ command to module 0. Without waiting for a response, the CPU sends an address and READ to module 1. Finally, the CPU sends an address and READ command to module 7. Then, the CPU actually reads from module 0. If the memory access time is 80 nanoseconds, the CPU can issue on command every 10 nanoseconds as it will take 80 nanoseconds to get back and read a given module.
Interrupts
Efficient management of Input / Output devices demands that these devices be able to signal the CPU when they are ready to initiate a data transfer. For an input device, this occurs when new data are in its input buffer. For an output device, this occurs when the device buffer is empty and the device can accept new data for later output. While easier to understand within an I/O context, interrupts can occur in other contexts.
- Errors and malfunctions.
- Page faults in a virtual memory system (these are hard to handle).
- Software interrupts or “traps” that allow user software to signal the Operating System. These differ slightly from standard procedure calls. Interrupts are either maskable (that is, the CPU can be set to ignore them) or nonmaskable. Generally, the only reason to mask interrupts occurs during that small time of program execution in which the CPU is beginning to process an interrupt. Improper masking of interrupts can cause a system to crash.
The MARIE Architecture
The MARIE has a 12–bit address space and a 16–bit addressable memory, so it supports 2 12 words of memory. This is 4K words, addressed 0 to 4,095 inclusive. It might be said to have 8 KB of memory, but it does not support byte addressing. Note: If the MARIE has a 12–bit address space, the MAR is a 12–bit register.
The MARIE Datapath
The MARIE datapath is a bit unusual in that it has a number of direct paths into each of the AC (accumulator) and ALU. This bus is internal to the CPU. Note the direct paths MBR AC and MBR ALU. This is an artifact of the use of a single bus internal to the CPU.
The MARIE Instruction Format
As noted above, the MARIE has a fixed word length and fixed instruction length. Each instruction is a 16–bit word with a 4–bit opcode and 12–bit address. The MARIE has two instruction sets: basic and advanced. We begin with a study of the basic instruction set and consider the advanced instructions later.
A Notational Problem
Consider the high–level assignment statement Y = X. Interpretation: Take the value at the address associated with the variable X. Place that value in the address associated with the variable Y. In courses on Computer Architecture and Assembly Language, the notation that appears to reference variables often specifies a memory address , not its contents. In the notation associated with control unit design (RTL – R egister T ransfer L anguage), this might appear as follows. MAR X // The address X is placed into the Memory Address Register MBR M[MAR] // The contents of this address are placed into the MBR AC MBR // The contents of the MBR are placed into the Accumulator MAR Y // The address Y is placed into the Memory Address Register MBR AC // The Accumulator is copied into the Memory Buffer Register M[MAR] MBR // The data are written into memory at address Y In this context, what appears to be a variable name is really an associated address. In this context, what appears to be a register name refers to the contents of that register.
The Common Fetch Cycle and a Definition
The PC is the Program Counter. It is a special purpose register in the CPU. The PC contains the address of the instruction to be executed next. Note that the Program Counter does not count anything. It just points to the next instruction. INTEL calls this the IP or Instruction Pointer , a much better name. The IR is the Instruction Register. It holds the binary representation of the machine language instruction currently being executed. A stored program computer functions by fetching instructions from the primary memory and executing those instructions. Here is the common fetch sequence. MAR PC // The Program Counter is copied into the MAR MBR M[MAR] // The contents of that address are placed into the MBR IR MBR // The instruction at that address is placed into the IR NOTE: AC MBR // The contents of the address are data IR MBR // The contents of the address form an instruction
How Fetch Really Works
In reality, the computer memory cannot respond quickly enough to effect the above fetch sequence. One must have one cycle during which memory is not accessed. MAR PC // The Program Counter is copied into the MAR WAIT // Wait for the memory to produce its results. MBR M[MAR] // The contents of that address are placed into the MBR IR MBR // The instruction at that address is placed into the IR I hate to waste time! What can be done during this WAIT cycle that does not involve memory? The answer comes from the fact that the most instruction most likely to be executed is the one following this instruction. MAR PC // The Program Counter is copied into the MAR PC (PC) + 1// Increment the PC to point to the next instruction. MBR M[MAR] // The contents of that address are placed into the MBR IR MBR // The instruction to be executed now is in the IR. // The address of the next instruction is in the PC. AGAIN: When an instruction is being executed, it is the address of the next instruction (in memory) that is in the PC.
Basic Instruction Set Definition
1. Load X // Load the contents of memory address X into the Accumulator. MAR X // Copy the memory address X into the MAR, the Memory // Address Register. This is the only way to address memory. MBR M[MAR] // Read memory and copy the contents of the address into // the Memory Buffer Register. AC (MBR) // Copy the contents of the MBR into the Accumulator. This is often abbreviated to AC M[X] 2. Store X // Store the contents of the Accumulator into memory address X MAR X // Place the address into the MAR MBR (AC) // Copy the accumulator into the MBR M[MAR] (MBR) // Write the MBR contents into memory at address X This is often abbreviated as M[X] (AC)
Basic Instruction Set Definition (Part 2)
3. Add X // Add the contents of memory address X to the Accumulator MAR X // Place the memory address into the MAR MBR M[MAR] // Read memory and place the contents into the MBR AC (AC) + (MBR) // Add the contents of the AC and MBR. Place in the AC. 4. Subt X // Subtract the contents of memory address X from the Accumulator. MAR X // Place the memory address into the MAR MBR M[MAR] // Read memory and place the contents into the MBR AC (AC) – (MBR) // Subtract MBR contents from AC contents. // Place result in the accumulator, AC. 5. Input AC (InREG) // Copy the contents of the input register into the AC.
