Solved Quiz for Computer Organization | CPSC 2105, Quizzes of Computer Architecture and Organization

Material Type: Quiz; Class: Computer Organization; Subject: Computer Science; University: Columbus State University; Term: Spring 2006;

Typology: Quizzes

Pre 2010

Uploaded on 08/04/2009

koofers-user-aew
koofers-user-aew 🇺🇸

10 documents

1 / 4

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
CPSC 2105 Introduction to Computer Organization
Quiz 9 Wednesday, April 19, 2006
Test key with answers and comments.
All questions in this test are based on the computer described below.
Main memory: 262, 144 bytes (256 KB or 218 bytes). Access time = 60 nanoseconds.
The memory is byte–addressable.
Cache The cache is 2–Way Set Associative.
The cache contains 256 sets (28 sets).
Each cache block contains 16 bytes (24 bytes).
The cache access time is 8 nanoseconds.
REMARK: The very unusual structure of this cache is due to my desire to have both the
word field and set field be a multiple of 4 bits in length. This allows the use
of hexadecimal digits for the word and set fields.
Viewed this way, the fields are:
Byte Offset in Block 1 hexadecimal digit
Set Number 2 hexadecimal digits
Tag 2 hexadecimal digits, beginning with
0, 1, 2, or 3.
NOTE: Hexadecimal digits normally represent 4 binary bits.
Two bit numbers can also be represented as hexadecimal digits.
00 is 0, 01 is 1, 10 is 2, and 11 is 3.
1. What is the format of a memory address as seen by the cache?
ANSWER: There are 18 address bits needed to access the memory.
Of these, the byte offset in the cache block is 4 bits
The cache set field is 8 bits
The tag is 18 – (4 + 8) 6 bits.
Bits 17 through 12 11 through 4 3 2 1 0
6 bits 8 bits 4 bits
Field Tag Set Byte Offset in Block
The address, containing 18 bits, can be represented as five hexadecimal digits, with the most
significant hex digit being either 0, 1, 2, or 3.
Quiz Key Page 1 of 4 pages Revised: 4/24/2006
pf3
pf4

Partial preview of the text

Download Solved Quiz for Computer Organization | CPSC 2105 and more Quizzes Computer Architecture and Organization in PDF only on Docsity!

CPSC 2105 Introduction to Computer Organization

Quiz 9 Wednesday, April 19, 2006

Test key with answers and comments. All questions in this test are based on the computer described below. Main memory: 262, 144 bytes (256 KB or 2^18 bytes). Access time = 60 nanoseconds. The memory is byte–addressable. Cache The cache is 2–Way Set Associative. The cache contains 256 sets (2^8 sets). Each cache block contains 16 bytes (2^4 bytes). The cache access time is 8 nanoseconds. REMARK: The very unusual structure of this cache is due to my desire to have both the word field and set field be a multiple of 4 bits in length. This allows the use of hexadecimal digits for the word and set fields. Viewed this way, the fields are: Byte Offset in Block 1 hexadecimal digit Set Number 2 hexadecimal digits Tag 2 hexadecimal digits, beginning with 0, 1, 2, or 3. NOTE: Hexadecimal digits normally represent 4 binary bits. Two bit numbers can also be represented as hexadecimal digits. 00 is 0, 01 is 1, 10 is 2, and 11 is 3.

  1. What is the format of a memory address as seen by the cache? ANSWER: There are 18 address bits needed to access the memory. Of these, the byte offset in the cache block is 4 bits The cache set field is 8 bits The tag is 18 – (4 + 8) 6 bits. Bits 17 through 12 11 through 4 3 2 1 0 6 bits 8 bits 4 bits Field Tag Set Byte Offset in Block The address, containing 18 bits, can be represented as five hexadecimal digits, with the most significant hex digit being either 0, 1, 2, or 3.

The next three questions assume the following sequence of memory accesses, beginning with an empty cache and issued in this exact order, with the top line (left to right) first: 00AB1 00AC2 01AB8 01AB9 01ABA 00AB2 00AB3 01ABC 01AC0 01AC4.

  1. a) What cache sets are accessed? b) What is the hit ratio displayed by this sequence of memory accesses? ANSWER: The division of the five hexadecimal address is 2 hex digits for the tag, 2 hex digits for the set, and one hex digit for the byte. a) Cache sets AB and AC are the only two sets accessed. b) We now follow the sequence of memory accesses. Access 00AB1 MISS Hits = 0 Misses = 1 Set Block 0 Block 1 Tag Contents Tag Contents AB 00 00AB0 through 00ABF empty Access 00AC2 MISS Hits = 0 Misses = 2 Set Block 0 Block 1 Tag Contents Tag Contents AB 00 00AB0 through 00ABF empty AC 00 00AC0 through 00ACF empty Access 01AB8 MISS Hits = 0 Misses = 3 Set Block 0 Block 1 Tag Contents Tag Contents AB 00 00AB0 through 00ABF 01 01AB0 through 01ABF AC 00 00AC0 through 00ACF empty NOTE: 01AB8 is a cache MISS even though it maps to set AB, a set that has a block filled. This is due to the fact that this memory reference has Tag = 01 and the block already in the set has Tag = 00. Access 01AB9 HIT Hits = 1 Misses = 3 Set Block 0 Block 1 Tag Contents Tag Contents AB 00 00AB0 through 00ABF 01 01AB0 through 01ABF AC 00 00AC0 through 00ACF empty
  1. What memory blocks will be in the cache after the last address has been accessed? ANSWER: By inspection, we have blocks 00AB, 00AC, 01AB, and 01AC. COMMENT: We have the following addresses in the cache. Set AB, Block 0 00AB0, 00AB1, 00AB2, 00AB3, 00AB4, 00AB5, 00AB6, 00AB7, 00AB8, 00AB9, 00ABA, 00ABB, 00ABC, 00ABD, 00ABE, 00ABF Set AB, Block 1 01AB0, 01AB1, 01AB2, 01AB3, 01AB4, 01AB5, 01AB6, 01AB7, 01AB8, 01AB9, 01ABA, 01ABB, 01ABC, 01ABD, 01ABE, 01ABF Set AC, Block 0 00AC0, 00AC1, 00AC2, 00AC3, 00AC4, 00AC5, 00AC6, 00AC7, 00AC8, 00AC9, 00ACA, 00ACB, 00ACC, 00ACD, 00ACE, 00ACF Set AC, Block 1 01AC0, 01AC1, 01AC2, 01AC3, 01AC4, 01AC5, 01AC6, 01AC7, 01AC8, 01AC9, 01ACA, 01ACB, 01ACC, 01ACD, 01ACE, 01ACF The answer to the question is based on the following observation: Set AB Block 0 Contains memory block 00AB Set AB Block 1 Contains memory block 01AB Set AC Block 0 Contains memory block 00AC Set AC Block 1 Contains memory block 01AC. Each memory block holds 16 bytes, as does each cache block. The memory address format Bits 17 through 4 3 2 1 0 14 bits 4 bits Field Memory Block Number Byte Offset in Block This differs from the memory address as seen by the cache, which is: Bits 17 through 12 11 through 4 3 2 1 0 6 bits 8 bits 4 bits Field Tag Set Byte Offset in Block
  2. What is the effective access time of the memory for this address sequence? ANSWER: TE = hTC + (1 – h)TP = 0.608 + 0.460 = 4.8 + 24 = 28.8 nanoseconds. COMMENT: If I applied your hit ratio (from problem 2) and got your answer, I awarded full credit.