Memory Part 1-Assembly Language Programming-Lecture Slides, Slides of Assembly Language Programming

This lecture was delivered by Mr. Gurpreet Verma at Cochin University of Science and Technology for Assembly Language Programming course. It includes: Components, Computer, Locality, SRAM, DRAM, Memory, Memory, Hierarchy, Parallelism, Locality, Processor

Typology: Slides

2011/2012

Uploaded on 07/26/2012

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Chapter 7.1 - Memory1 1
The Five Classic Components of a Computer
Today’s Topics:
Locality and Memory Hierarchy
SRAM Memory Technology
DRAM Memory Technology
Memory Organization
The Big Picture: Where are We Now?
Control
Datapath
Memory
Processor
Input
Output
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Download Memory Part 1-Assembly Language Programming-Lecture Slides and more Slides Assembly Language Programming in PDF only on Docsity!

Chapter 7.1 - Memory

•^

The Five Classic Components of a Computer

-^

Today’s Topics:

  • Locality and Memory Hierarchy– SRAM Memory Technology– DRAM Memory Technology– Memory Organization

The Big Picture: Where are We Now?

Control Datapath

Memory

Processor

Input Output

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Chapter 7.1 - Memory

Technology Trends (from 1st lectures)

DRAM

Year

Size

Cycle Time

64 Kb

250 ns

256 Kb

220 ns

1 Mb

190 ns

4 Mb

165 ns

16 Mb

145 ns

64 Mb

120 ns

Capacity

Speed

(latency) Logic:

in 3 years

in 3 years

DRAM:

in 3 years

in 10 years

Disk:

in 3 years

in 10 years

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Chapter 7.1 - Memory

The Goal: Illusion of Large,

Fast, Cheap Memory

-^

Fact:

Large memories are slowFast memories are small

-^

How do we create a memory that is large, cheap andfast (most of the time)?

  • Hierarchy– Parallelism

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Chapter 7.1 - Memory

Memory Hierarchy of a

Modern Computer System

-^

By taking advantage of the principle of locality:

  • Present the user with as much memory as is available in the

cheapest technology.

  • Provide access at the speed offered by the fastest technology.

Control

Datapath

Secondary

Storage(Disk)

Processor

Registers

Main Memory(DRAM)

SecondLevelCache(SRAM)

On-Chip Cache

TertiaryStorage(Tape)

ThirdLevelCache (SRAM)

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Chapter 7.1 - Memory

Memory Hierarchy:

Why Does It Work? Locality!

•^

Temporal Locality (Locality in Time):

Keep most recently accessed data items closer to the processor

-^

Spatial Locality (Locality in Space):

Move blocks consisting of contiguous words to the upper levels

Lower Level

Memory

Upper Level

Memory

To Processor

From Processor

Blk X

Blk Y

Address Space

n^

Probabilityof reference

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Chapter 7.1 - Memory

Example: 1 KB Direct Mapped

Cache With 32 Byte Blocks

-^

For a 2

N

byte cache:

  • The uppermost (32 -

N

) bits are always the Cache Tag

  • The lowest M bits are the Byte Select (Block Size = 2

M

Cache Index

0 1 2 3

Cache Data

Byte 0

0

4

31

Cache Tag

Example: 0x

Ex: 0x

Stored as partof the cache “state”0x

Valid Bit

31

Byte 1

Byte 31

Byte 32

Byte 33

Byte 63

Byte 992

Byte 1023

Cache Tag

Byte Select

Ex: 0x

9

Block address

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Chapter 7.1 - Memory

How Is the Hierarchy Managed?

Registers

Memory

–by compiler (programmer?)

cache

memory

–by the hardware

memory

disks

–by the hardware and operating system (virtual memory)–by the programmer (files)

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Chapter 7.1 - Memory

Memory Hierarchy Technology

-^

Random Access:

  • “Random” is good: access time is the same for all locations– DRAM: Dynamic Random Access Memory -^

High density, low power, cheap, slow

-^

Dynamic: need to be “refreshed” regularly

  • SRAM: Static Random Access Memory -^

Low density, high power, expensive, fast

-^

Static: content will last “forever”(until lose power)

-^

“Non-so-random” Access Technology:

  • Access time varies from location to location and from time to time– Examples: Disk, CDROM, DRAM page-mode access -^

Sequential Access Technology: access time linear in location( e.g.

,Tape)

-^

We will concentrate on random access technology

  • The Main Memory: DRAMs + Caches: SRAMs

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Chapter 7.1 - Memory

Random Access Memory

(RAM) Technology

The term comes from the way data is accessed in this memory, and symbolizes the

possibility to access any part of the memory at any given time. The contrarywould be sequential memory, which mostly has a meaning in tape backupsituations. Early computers also used drum memory, which was sequential (kindof). All computer memory modules used in computers today are of the RAM type. This

type of memory can be subdivided into two main groups:

  • SRAM - Static RAM• DRAM - Dynamic RAMThe difference between the two is that as long as power is maintained on the

memory modules the DRAM will hold it's information. The content of DRAMmemory disappears from the memory within milliseconds, so in order to maintainit's data it has to be refreshed periodically. This makes the DRAM memory muchslower than the SRAM. The computer memory you usually see are a form of DRAM, like SDRAM, and

DDR-SDRAM. Because SRAM doesn't have to be refreshed it is much faster thanDRAM and also much more expensive. The speed advantage of SRAM means that it is used in the computers cache

memory, which is a small amount of high speed SRAM memory mounted close toor on the processor itself.

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Chapter 7.1 - Memory

Random Access Memory

SDRAM; •^

Short for

Synchronous DRAM,

a type of DRAM that can run at much higher

clock speeds than conventional memory. SDRAM actually synchronizesitself with the CPU's bus and is capable of running at 133 MHz, DDR (Double Data Rate) is a technology used in some SDRAM memories to

increase the speed at which data can be written/retrieved from the memory.

-^

DDR increase the transfer rate by sending/receiving memory data twice perclock cycle. This give a theoretical multiplication of transfer speed by two. DDR2-SDRAM maintains the same core functions, transferring 64 bits of data twice

every clock cycle for an effective transfer rate twice that of the front-side bus (FSB)of a computer system, and an effective bandwidth equal to its speed x 8.

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Chapter 7.1 - Memory

-^

“Out-of-Core”, “In-Core,” “Core Dump”?

-^

“Core memory”?

-^

Non-volatile, magnetic

-^

Lost to 4 Kbit DRAM (today using 512 Mbit DRAM)

-^

Main Memory Deep Background Access time 750 ns, cycle time 1500-3000 ns

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Chapter 7.1 - Memory

1-transistor Memory Cell (DRAM)

-^

Write:

    1. Drive bit line.– 2. Select row. -^

Read:

    1. Precharge bit line to Vdd/2.– 2. Select row.– 3. Cell and bit line share charges. -^

Very small voltage changes on the bit line.

    1. Sense (fancy sense amp). -^

Can detect changes of ~

6

electrons.

    1. Write: restore the value. -^

Refresh.

    1. Just do a dummy read to every cell.

row select

bit

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Chapter 7.1 - Memory

DRAM Performance

-^

A 60 ns (

t RAC

) DRAM can.

  • perform a row access only every 110 ns (

t RC

  • perform column access (

t CAC

) in 15 ns, but time between column

accesses is at least 35 ns (

t PC

-^

In practice, external address delays and turning around busesmake it 40 to 50 ns.

-^

These times do not include the time to drive the addresses off themicroprocessor, nor the memory controller overhead.

  • Drive parallel DRAMs, external memory controller, bus to turn

around, SIMM module, pins…

  • 180 ns to 250 ns latency from processor to memory is good for a “

ns” (

t RAC

) DRAM.

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Chapter 7.1 - Memory

Something New: Structure ofTunneling Magnetic Junction

°

Tunneling Magnetic Junction RAM (TMJ-RAM)

Speed of SRAM, density of DRAM, non-volatile (no refresh) - “Spintronics”: combination quantum spin and electronics - Same technology used in high-density disk-drives

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