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This lecture was delivered by Mr. Gurpreet Verma at Cochin University of Science and Technology for Assembly Language Programming course. It includes: Abstract, Crtical, Perform, Meaning, Connections, Calculate, Fetch, jump, Except, Datapath, Store, Contol
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Chapter 5.2 - Processor Design 2
imm
ALUctr
Clk RegWrbusW^32
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst
Extender
Mux
32
imm
ALUSrc
ExtOp
Mux MemtoReg
Clk Data In
WrEn
Adr DataMemory MemWr ALU
Equal
Instruction<31:0>
Imm Rd Rt Rs
Adder Adder
(^00) PC Clk^
Mux
nPC_sel
PC Ext
Adr Inst Memory
Chapter 5.2 - Processor Design 2
-^
Register file and ideal memory:
Address valid => Output valid after “access time.”
Critical Path (Load Operation) =
PC’s Clk-to-Q +Instruction Memory’s Access Time +Register File’s Access Time +ALU to Perform a 32-bit Add +Data Memory Access Time +Setup Time for Register File Write +Clock Skew
Clk
5 Rw
Ra
Rb
32 32-bitRegisters Rd
Clk DataAddressDataIn
IdealDataMemory
Instruction
Instruction
Address
Ideal InstructionMemory^ Clk
Rs^5
Rt^5
Imm^16
Next Address
Chapter 5.2 - Processor Design 2
DataOut
(^5) Clk Rw
Ra
Rb
32 32-bitRegisters Rd
Clk DataAddressDataIn
IdealDataMemory
Instruction
Instruction
Address
Ideal InstructionMemory^ Clk
Rs^5
Rt^5
Next Address
Conditions
Chapter 5.2 - Processor Design 2
-^
Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit
-^
We have everything except control signals (underline)^ – Today’s lecture will show you how to generate the control signals
ALUctr
Clk busW
RegWr 32
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst
Extender
Mux
Mux
imm
ALUSrc
ExtOp
MemtoRegMux
Clk
Data In
WrEn
32
Adr DataMemory
MemWr
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
Imm Rd Rs Rt
nPC_sel
Chapter 5.2 - Processor Design 2
-^
-^
-^
°^
°^
°^
°^
ALUctr
Clk RegWr busW^32
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst
Extender
Mux
32
imm
ALUSrc
ExtOp
Mux MemtoReg
Clk Data In
WrEn
Adr DataMemory MemWr ALU
Equal
Chapter 5.2 - Processor Design 2
mem[PC]
Fetch the instruction from memory
R[rd]
R[rs] + R[rt]
The actual operation
PC
PC + 4
Calculate the next instruction’s address
op
rs^
rt^
rd
shamt
funct
6 bits
6 bits
5 bits
5 bits
5 bits
5 bits
Chapter 5.2 - Processor Design 2
-^
op
rs^
rt^
rd
shamt
funct
ALUctr = Add
Clk RegWr = 1 busW
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst = 1
Extender
Mux
Mux
imm
ALUSrc = 0
ExtOp = x
Mux MemtoReg = 0
Clk
Data In
WrEn
32
Adr DataMemory
MemWr = 0
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
Imm Rd Rs Rt
nPC_sel= +
Chapter 5.2 - Processor Design 2
-^
PC
PC + 4
Adr Inst Memory
Adder
Adder
Clk
Mux
nPC_sel
imm
Instruction<31:0>
Chapter 5.2 - Processor Design 2
The Single Cycle Datapath during Or Immediate
-^
op
rs^
rt^
immediate
ALUctr = Or
Clk busW
RegWr = 1^32
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst = 0
Extender
Mux
Mux
imm
ALUSrc = 1
ExtOp = 0
Mux MemtoReg = 0
Clk
Data In
WrEn
32
Adr DataMemory
MemWr = 0
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
Imm Rd Rs Rt
nPC_sel= +
Chapter 5.2 - Processor Design 2
-^
op
rs^
rt^
immediate
ALUctr =
Add
Clk busW
RegWr = 1^32
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst = 0
Extender
Mux
Mux
imm
ALUSrc = 1
ExtOp = 1
Mux MemtoReg = 1
Clk
Data In
WrEn
32
Adr DataMemory
MemWr = 0
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
Imm Rd Rs Rt
nPC_sel= +
Chapter 5.2 - Processor Design 2
Instruction<31:0>
-^
op
rs^
rt^
immediate
ALUctr =
Add
Clk RegWr = 0 busW
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst = x
Extender
Mux
Mux
imm
ALUSrc = 1
ExtOp = 1
Mux MemtoReg = x
Clk
Data In
WrEn
32
Adr DataMemory
MemWr = 1
InstructionFetch Unit
Clk
Zero
Imm Rd Rs Rt
nPC_sel= +
Chapter 5.2 - Processor Design 2
op
rs^
rt^
immediate
ALUctr =Sub
Clk RegWr = 0 busW
busA busB^32 5
Rw
Ra
Rb
32 32-bitRegisters
Rs Rt
Rt
Rd
RegDst = x
Extender
Mux
Mux
imm
ALUSrc = 0
ExtOp = x
Mux MemtoReg = x
Clk
Data In
WrEn
32
Adr DataMemory
MemWr = 0
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
Imm Rd Rs Rt
nPC_sel= “Br”
Chapter 5.2 - Processor Design 2
ALUctr
RegDst
ALUSrc
ExtOp
MemtoReg
MemWr
Zero
Instruction<31:0>
Imm
Rd Rs
Rt
nPC_sel
Adr Inst Memory
Op
Fun
RegWr
Chapter 5.2 - Processor Design 2
inst
Register Transfer
R[rd]
R[rs] + R[rt];
ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”SUB
R[rd]
R[rs] – R[rt];
ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”ORi
R[rt]
R[rs] + zero_ext(Imm16);
ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”LOAD
R[rt]
MEM[ R[rs] + sign_ext(Imm16)];
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”,
MemtoReg,
RegDst = rt, RegWr,
nPC_sel = “+4”
MEM[ R[rs] + sign_ext(Imm16) ]
R[rs];
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”BEQ
if ( R[rs] == R[rt] ) then PC
PC + sign_ext(Imm16)] || 00 else PC
nPC_sel = “Br”, ALUctr = “sub”
