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Module Learning Objectives, Students should be able to:
GPIO
Microcontroller Peripherals
Module 6: Part 1 (M6.1)
Define microcontroller peripheral hardware and describe basic
functions of typical microcontroller peripherals
Explain the relationship between the Freedom KL25Z evaluation
board, the Kinetis MKL25Z128VLK4 microcontroller, and the ARM
Cortex-M0 core
Describe how peripheral hardware is memory mapped
ECE 331
Prof. Nihar Mahapatra
(adapted from Prof. A. Mason’s lecture notes; other sources listed at the end)
Microcontroller Peripherals
The processor (CPU) is the “core” of a microcontroller o executes instructions o “brains” of a controller Another major component of a μcontroller is the peripheral hardware o Peripheral=exterior; bordering; “on the side”
- peripheral hardware = outside of the core (CPU)
- aka I/O Devices (from architecture discussion) o Provides functional capability within hardware blocks
- controlled by software, but operating independent of software allows a controller to do multiple tasks simultaneously Typical μcontroller peripheral hardware o General purpose I/O (GPIO)
- digital input/output pins organized into ports o Timer(s) and time-controlled functions o Interrupt controller o Communication ports, e.g., SPI, USB o Analog-to-digital converter M6: GPIO 2
Example peripheral hardware
TI LM3S811 Microcontroller o Core = ARM Cortex M o Systick timer; timer ports; PWM o Nested Vectored Interrupt Controller (NVIC) o GPIO A-E (shares pins with other functions) o Comm ports (SSI, UART, JTAG, I^2 C) o Analog comparator TI LM3S811 Microcontroller Block Diagram M M M M M
ECE 331 Evaluation Board - FRDM-KL25Z
FRDM-KL25Z board o Kinetis MKL25Z 128 VLK 4 processor o On-board sensors:
- 3 - axis accelerometer
- capacitive touch slider o On-board actuator: RGB LED o I/O headers o USB Freescale Kinetis MKL25Z 128 VLK4 processor o 48 MHz 32-bit Cortex M0+ Processor Core o 128 kB Flash ROM, 16 kB SRAM o System Peripherals
- low power modes
- COP watchdog timer
- interrupt controller o Clocks
- crystal oscillator
- 1 kHz low power clock o Peripheral I/O Modules
- 66 general-purpose input/output (GPIO) multiplexed function with features below
- Communication interfaces
- Analog modules
- Timers Freedom KL25Z development board Kinetis MKL25Z128VLK microcontroller ARM Cortex M0+ 3 size of Flash ROM (128kB) package identifier (LK=80-pin LQFP package) Module
Kinetis MKL25Z128VLK4 Peripheral Devices
66 GPIO pins (from 5 32-bit ports) o not all port bits go to pins Communication Interfaces o USB full-/low-speed
- with On-the-Go controller, on-chip transceiver and 5V to 3.3V regulator o Two UART modules o One low power UART module o Two 8 - bit SPI modules o Two I^2 C module Timer Modules o Timer/PWM (TPM) modules
- One 6-channel
- Two 2 - channel o Periodic interrupt timers (PIT) o 16 - bit low-power timer (LPTMR) o Real time clock (RTC) Analog Modules o 24 - channel, 16-bit SAR ADC o 12 - bit DAC o Analog comparator
- with 6 - bit reference voltage DAC M6: GPIO 4 Kinetis KL25 Family Functions Module Module Module
I/O Ports M6: GPIO
7 I/O Ports (Pins) for KL25ZVLK 66 GPIO pins o Port A (PTA), 15 pins o Port B (PTB), 12 pins o Port C (PTC), 16 pins o Port D (PTD), 8 pins o Port E (PTE), 16 pins Alternate Functions o All GPIO pins can be configured as (connected to) several other peripheral functions o Alternate pin function set by MUX bits in the Pin Control Register (PORTx_PCRn)
- one register for each bit/pin
- MUX bits select from Alt0 – Alt7 functions Default Functions o Most GPIO pins default to their Alt function SPI SPI I2C I2C UART UART UART ADC DAC Compare Timer Port A Port B Port C Port D Port E
Pin ALT Function Table: Ports A & B
Port A
Port B
M6: GPIO 8 8 ALT function options
Pin ALT Function Table: Ports C & D
Port C
Port D
9 8 ALT function options
Pin ALT Function Table: Port E
Port E
Selection of ALT function
o Pin n Control Register (PORTx_PCRn)
- bits 10:8 = MUX
- select ALT0 – ALT o one register for each pin (n) of each port (x) M6: GPIO 10 8 ALT function options
Coding PCR Setup
Writing configuration registers o directly writing to configuration registers like PCR can be dangerous
- storing value to a register will write (0 or 1) to all bits of the register but you often only want to change a subset of bits
- could change bits that should not be changed may have been set to different value by other code Read-Modify-Write o solution to the problem above o first: read current value from configuration register o then: modify only the bits you want to set (using ORRS) or clear (using BICS) o finally: write modified value back to configuration register o only necessary when a register contains multiple configuration parameters that may have been set by other parts of the program
- don’t need to do this, e.g., with a port data output register 13 Example: Assembly code for setting Port A pins 1 & 2 (PTA1, PTA2) to ALT2 function (UART0) using read-modify-write Example 2: Set Port D pin 1 to GPIO using read-modify-write
Bit Mask Table
Bit x o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 o 11 o 12 o 13 o 14 o 15 o 16 o 17 o 18 o 19 o 20 o 21 o 22 o 23 o 24 o 25 o 26 o 27 o 28 o 29 o 30 o 31 M6: GPIO 14
Examples
Binary mask for bits 1 and 5
obit 1 = 2_0000. obit 5 = 2_0001. othus mask for bits 1 & 5 = 2_0001.
Hex bit mask for bits 14 and 22
obit 14 = 0x0000. obit 22 = 0x0040. othus mask for bits 14 & 22 = 0x0040.
Hex bit mask for bits 31, 23, 9, 8 & 2
obit 31 = 0x8000. obit 23 = 0x0080. obit 09 = 0x0000. obit 08 = 0x0000. obit 01 = 0x0000. othus combined mask = 0x8080. Dec, 2x o 1 o 2 o 4 o 8 o 16 o 32 o 64 o 128 o 256 o 512 o 1024 o 2048 o 4096 o 8192 o 16k o 32k o 64k o 128k o 256k o 512k o 1M o 2M o 4M o 8M o 16M o 32M o 64M o 128M o 256M o 512M o 1G o 2G Hex Mask o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x o 0x1. o 0x2. o 0x4. o 0x8. o 0x10. o 0x20. o 0x40. o 0x80. o 0x100. o 0x200. o 0x400. o 0x800. o 0x1000. o 0x2000. o 0x4000. o 0x8000. Binary o 0000. o 0000. o 0000. o 0000. o 0001. o 0010. o 0100. o 1000. o etc…
Module Learning Objectives, Students should be able to:
GPIO
Parallel I/O Ports
Module 6: Part 2 (M6.2)
Describe the function and organization of general purpose parallel I/O ports Identify and describe GPIO port configuration registers Use masks to set and clear bits of port configuration registers Write ASM and C code to read/write GPIO ports
ECE 331
Prof. Nihar Mahapatra
(adapted from Prof. A. Mason’s lecture notes; other sources listed at the end)
GPIO Configuration
One function of most port pins is general purpose input/output (GPIO) o KL25ZVLK4 GPIO Pins (66 total)
- Port A (PTA), 15 pins
- Port B (PTB), 12 pins
- Port C (PTC), 16 pins
- Port D (PTD), 8 pins
- Port E (PTE), 16 pins Configuring GPIO requires the following steps oEnable Port Clocks
- activate port by enabling its clock port clocks disabled by default (reset) oSet Pin Function to GPIO
- configure multi-tasking port to the GPIO function oSet Pin Data Direction
- pins can be input or output, as determined by data direction register M6: GPIO 16 In KL25Z, System Integration Module (SIM) o contains many bit-fields for selecting the clock source and dividers for various module clocks System Clock Gate Control Reg. (SIM_SCGC5) o controls (gates) clocks to ports A-E Enable Port Clocks SIM_SCGC SIM_SCGC Address: 0x4004. Bits 13:9 control clocks to Ports E:A 0: disable clock 1: enable clock
Input and Output Pins
Input Pins o schematic o read only
- read from pin’s port address returns values on all pins at the time of the read instruction
- write to input pin does nothing o valid logic voltages for VDD = 3.5V
- 0 to ~1.1V logic 0
- ~2.5-3.5V logic 1 19
Readable Output Pin
oalthough you can’t write to an input pin, on most microcontrollers output pins are readable oschematic owrite to output port address places value on GPIO output pins oread from port address returns values on output pins (and input pins) at the time of the read instruction
but can a Port be both input &
output?
D Q Output Port Write to port address Processor Read from port address Bus n n tri-state: enabled by read instruction output data latch; stores data on write to port tri-state: enabled by read instruction, even for output pins
Port Direction & Port Data Registers
Bidirectional Pin Schematic o output tri-state driver “gates” output signal
- disabled for input pins
- enabled for output pins Pin direction (input/output) set by data direction register (DDR) o each port has one register for DDR o each DDR has one bit for direction of each pin M6: GPIO 20 Port Data Registers o each port (A-E) has a block of data registers to read, write, and set direction o each port data registers block has a base address
- Port Base Address PTA 400F_F PTB 400F_F PTC 400F_F PTD 400F_F0C PTE 400F_F o each port data registers block contains the following functional registers
- each 32-bit reg. has fixed offset from base
- GPIO Register Offset (from base) Data Output PDOR 0x Set Output PSOR 0x Clear Output PCOR 0x Toggle Output PTOR 0x0C Data Input PDIR 0x Data Direction PDDR 0x Input/Output Port D Q Write to port direction register Direction bits D Q Write to port address Processor Read from port address Bus n n n n n (^) 1 means output 0 means input output driver enabled for each pin defined as output data direction control bit Address Register name Short name 400F_F040 Port B Data Output Register (PTB_PDOR) 400F_F044 Port B Set Output Register (PTB_PSOR) 400F_F048 Port B Clear Output Register (PTB_PCOR) 400F_F04C Port B Toggle Output Register (PTB_PTOR) 400F_F050 Port B Data Input Register (PTB_PDIR) 400F_F054 Port B Data Direction Register (PTB_PDDR) example data reg. block for Port B PTB base: 400F.F
- PDDR offset: 14 PTB_PDDR: 400F.F
Data Direction Register
Data direction register (DDR) o each port has one register for data direction o each DDR has one bit for direction of each pin (controls output tri-state driver)
- 0 = input ;disables output driver
- 1 = output ; enables output driver 21 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PORTx_DDR (PTx_PDDR) biti = direction of pini Reset value = 0 (input)
Example assembly code to set DDR
Set Port B pins 0 - 5 and 14 - 15 as
output, all others as inputs
PTB_BASE EQU 0x400FF PDDR EQU 0x14 ;data dir. offset LDR R0,=0x0000C03F ;2_00000000.00000000.11000000. ;= 0x0000.C03F LDR R1,=PTB_Base STR R0,[R1,#PDDR]
Is this read-modify-write?
M6: GPIO 22
Same example using
Read-Modify-Write
PTB_BASE EQU 0x400FF PDDR EQU 0x14 ;data dir. offset LDR R0,=0x0000C03F ; 2_00000000.00000000.11000000. ;= 0x0000.C03F LDR R1,=PTB_Base LDR R2,[R1,#PDDR] ;read ORRS R2, R0 ;modify STR R2,[R1,#PDDR] ;write compiler will substitute EQU value here looking at the binary may be necessary declare variables in code header with EQU 15,14…...5,4,3,2,1,0 = 1’s
Example ASM Code: KL25Z LEDs
KL25Z RGB-LED
o one GPIO pin for each light color Assembly EQU directives o equate addresses to “easy to remember” terms Enable Port Clock 25 Set Pins to GPIO (ALT1 function) o write to PCR MUX bits as shown above Set Pin Data Direction o set PTB18, PTB19, PTD1 to outputs
Example ASM Code: KL25Z LEDs
KL25Z RGB-LED
o one GPIO pin for each light color Start by turning LEDs off o written as subroutine
- as were all setup routines on last page M6: GPIO 26 Main Program o Call subroutines o Setup for changing light colors o Example light color settings
References
J.W. Valvano, Introduction to ARM Cortex-M Microcontrollers
(Embedded Systems Vol. 1), 4th^ Ed, 2013, ISBN: 978-
J. Yiu, The Definitive Guide to the ARM Cortex-M0 , Elsevier,
2011, ISBN: 978- 0 - 12 - 385477 - 3.
J. Yiu, The Definitive Guide to ARM Cortex-M0 and Cortex-M0+
Processors , Elsevier, 2 nd^ Edition, 2015, ISBN: 978 - 0 - 12 -
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