Preparation Exercises with Solutions on Microprocessors - Study Guide | ECE 331 | Study notes Electrical and Electronics Engineering

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ECE 331 Preparation Exercise 8 Solutions

Please refer to Modules 6-7 course notes to answer the following questions.

1. What does GPIO stand for?

general purpose input / output, which defines a digital I/O pin whose value (0 or 1) can

be read or written, in contrast to pins with specific analog, serial, etc. functional

attributes.

2. List the peripheral modules (hardware functions), besides GPIO, on the Kinetis MKL25Z128VLK4

microcontroller.

Serial communication blocks: USB, UART (3), SPI (2), I2C (2)

Timer blocks: Timer/PWM (3), Periodic interrupt timer, Low-power timer, Real time clock

Analog blocks: Analog-to-digital converter, Digital-to-analog converter, Analog

comparator

3. Briefly describe what it means to say peripheral registers are “memory mapped”.

All peripheral function/configuration registers have a unique address in the controller

memory space. This allows those registers to be read/written using standard

instruction, just like reading/writing normal memory.

4. Each peripheral module can be routed to pins on multiple ports. What controls the routing of peripheral

functions to specific pins? In other words, how is the function of a pin set?

Each pin can be assigned to one of eight “alternate” functions using the 3-bit MUX field

of each pin’s PORTx_PCRn register.

5. Pin Control Registers (PCR) contains several fields to configure pin features. List and briefly describe the

fields/features discussed in class. Note some were covered during lecture for Module 6 and others for

Module 7.

Each PORTx_PCRn register has fields for: Interrupt status flag, Interrupt

configuration, Pin alt-function (MUX) control.

Other useful functions not discussed in ECE331 include: Drive strength enable, Pull

up/down enable, and Pull up/down select.

6. What is the base address for each of the following GPIO configuration registers? Note: you do not need to

remember these addresses for the exam, but you should know where to find them in the course notes and

understand how GPIO configuration is distributed over various registers.

a) Port B PCR

b) Port D GPIO (DDR, DOR, etc.)

c) Port C Clock Gate

a) Base address of Port B PCR is PORTB_PCR0 = 0x4004.A000

b) PORTD_GPIO base = 0x400F.F0C0

c) All port clock gates are in SIM_SCGC5 = 0x4004.8038

7. Each GPIO port has a “maskable” clock, meaning it can be enabled or disabled (gated). Are the clocks to

each GPIO port enabled or disabled by default (at reset)?

The reset value on bits 5:0 of regiseter SIM_SCGC5 are 0, thus all clocks are disabled

by default.

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ECE 331 Preparation Exercise 8 Solutions

Please refer to Modules 6-7 course notes to answer the following questions.

What does GPIO stand for? general purpose input / output , which defines a digital I/O pin whose value (0 or 1) can be read or written, in contrast to pins with specific analog, serial, etc. functional attributes.
List the peripheral modules (hardware functions), besides GPIO, on the Kinetis MKL25Z128VLK microcontroller. Serial communication blocks: USB, UART (3), SPI (2), I^2 C (2) Timer blocks: Timer/PWM (3), Periodic interrupt timer, Low-power timer, Real time clock Analog blocks: Analog-to-digital converter, Digital-to-analog converter, Analog comparator
Briefly describe what it means to say peripheral registers are “memory mapped”. All peripheral function/configuration registers have a unique address in the controller memory space. This allows those registers to be read/written using standard instruction, just like reading/writing normal memory.
Each peripheral module can be routed to pins on multiple ports. What controls the routing of peripheral functions to specific pins? In other words, how is the function of a pin set? Each pin can be assigned to one of eight “alternate” functions using the 3-bit MUX field of each pin’s PORTx_PCRn register.
Pin Control Registers (PCR) contains several fields to configure pin features. List and briefly describe the fields/features discussed in class. Note some were covered during lecture for Module 6 and others for Module 7. Each PORTx_PCRn register has fields for: Interrupt status flag, Interrupt configuration, Pin alt-function (MUX) control. Other useful functions not discussed in ECE331 include: Drive strength enable, Pull up/down enable, and Pull up/down select.
What is the base address for each of the following GPIO configuration registers? Note: you do not need to remember these addresses for the exam, but you should know where to find them in the course notes and understand how GPIO configuration is distributed over various registers. a) Port B PCR b) Port D GPIO (DDR, DOR, etc.) c) Port C Clock Gate a) Base address of Port B PCR is PORTB_PCR0 = 0x4004.A b) PORTD_GPIO base = 0x400F.F0C c) All port clock gates are in SIM_SCGC5 = 0x4004.
Each GPIO port has a “maskable” clock, meaning it can be enabled or disabled (gated). Are the clocks to each GPIO port enabled or disabled by default (at reset)? The reset value on bits 5:0 of regiseter SIM_SCGC5 are 0, thus all clocks are disabled by default.

Utilizing read-modify-write operation, write an ASM code segment to turn on clocks to Port B and Port D without affecting any other port clocks. You can assume SIM_SCGC5 EQU 0x40048038 is defined previously. SIM_SCGC5 EQU 0x LDR R0, =SIM_SCGC LDR R1, [R0] ;READ LDR R2, =0x1400 ;clock gate mask for PTB, PTD ORRS R1, R2 ;MODIFY, bit-set to enable only bits in mask above STR R1, [R0] ;WRITE
Port D only has 8 active pins (bits 0 – 7). Write the ASM code segment necessary to set all odd bits/pins (1,3,5,7) of Port D as outputs and all even bits (including bit 0) as inputs. Since you have been asked to assign direction to ALL pins, you do not need to employ read-modify-write. Assume the following variables have been assigned previously in code and use these variables in your code: PTD_BASE EQU 0x400FF0C0 ;port D GPIO base PDDR EQU 0x14 ;data direction offset

LDR R0, =PTD_BASE LDR R1, =2_00000000000000000000000010101010 ; =0xAA ;desired DDR value; 1 = output (odd bits), 0 = input (even bits) STR R1, [R0,#PDDR]

Describe the main differences between an internal electronic clock oscillator and:

a) a crystal-based resonating clock Internal clock is less stable (precise), lower cost, lower size, and lower power b) a PLL PLL has programmable frequency, is more precise, but requires time to power up

The KL25Z controller has several high-speed clock sources including a 4MHz IRC, an FLL, a PLL, and an external-crystal-based oscillator (OSCCLK). Identify which of these clock sources, IRC, FLL, PLL, or OSCCLK best matches the following characteristics. a) requires an external crystal oscillator OSCCLK b) is the active clock source after reset FLL c) produces a fixed 4MHz clock IRC d) has a very accurate frequency OSCCLK and PLL (PLL uses OSCCLK as an input source) e) generates a wide range of clock frequencies All. All clock sources are routed through dividers in the SIM module to generate a wide range of frequencies.
Consider a generic microcontroller timer unit with a 16-bit count-down counter operating with a 16MHz clock: a) How many unique values can the timer unit hold? 216 = 65,

Preparation Exercises with Solutions on Microprocessors - Study Guide | ECE 331, Study notes of Electrical and Electronics Engineering

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Download Preparation Exercises with Solutions on Microprocessors - Study Guide | ECE 331 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!

ECE 331 Preparation Exercise 8 Solutions

Please refer to Modules 6-7 course notes to answer the following questions.