Machine Cycles and Timing Diagrams in 8086 Microprocessor, Lecture notes of Microprocessors

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TIMING DIAGRAMS

MACHINE CYCLE or BUS CYCLE or INSTRUCTION

CYCLE

■ (^) Time taken by processor to execute an instruction ■ (^) Typically, all processors utilizes the following 5 stage cycles: ■ (^) Fetch instruction from main memory ■ (^) Decode the instruction ■ Fetch data from main memory ■ (^) Execute Instruction ■ Store result

MACHINE CYCLE or BUS CYCLE or INSTRUCTION

CYCLE

■ A machine (bus) cycle consists of at least four clock

cycles, called T states.

■ A specific, defined action occurs during each T state

(labeled T1 – T4)

• (^) T1 : Address is output
• (^) T2 : Bus cycle type (Mem/IO, read/write)
• (^) T3 : Data is supplied
• (^) T4 : Data latched by CPU, control signals removed

■ Why are there T states?

• (^) In the 8086/8088, the address and data lines are multiplexed.
• (^) The microprocessor needs time to change the signals during each bus cycle.
• (^) Memory devices need time to decipher the address value and then read/write the data

MACHINE CYCLE or BUS CYCLE or INSTRUCTION

CYCLE

TIMING DIAGRAM FOR READ CYCLE

TIMING DIAGRAM FOR READ CYCLE

TIMING DIAGRAM FOR READ CYCLE

TIMING DIAGRAM FOR READ CYCLE

SUMMARY ■ (^) T1 : 1st^ clocking period

• (^) address of memory or I/O : sent out via address bus
• control signal ALE, DT/R’, M/IO’(IO/M’) : output ■ (^) T2 : issue RD’ or WR’, DEN’
• in case of write : data to be written appear on data bus ■ (^) READY : sampled at the end of T
• if READY is low at end of T2 : T3 becomes a wait state(Tw) ■ (^) if read bus cycle : data bus is sampled at end of T ■ (^) T4 :
• (^) all bus signals : deactivated in preparation for next bus cycle
• (^) μP sampled data bus for data that read from M or I/O
• trailing edge of WR’ : transfer data to memory or I/O

TIMING DIAGRAM FOR READ CYCLE

8086 Min Mode Read Cycle

ADDRESS, DATA & CONTROL BUSES