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Microprogrammed Control
MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Design of Control Unit
• Microinstruction Format
• Nanostorage and Nanoprogram
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Microprogrammed Control - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization
Microprogrammed Control, Control Memory, Sequencing Microinstructions, Microprogram Example, Design of Control Unit, Microinstruction Format, Nanostorage and Nanoprogram are the key points of this lecture.
Typology: Slides
2011/2012
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MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Design of Control Unit
• Microinstruction Format
• Nanostorage and Nanoprogram
COMPARISON OF CONTROL UNIT IMPLEMENTATIONS
Implementation of Control Unit
Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Microprogram
I R
Status F/Fs
Control Data
Combinational
Logic Circuits
Control
Points
CPU
Memory
Timing State
Ins. Cycle State
Control Unit's State
Status F/Fs
Control Data
Next Address
Generation
Logic
C
S
A
R
Control
Storage
(μ-program
memory)
M e m o r y
I R
C
S
D
R
C
P
s
D CPU
}
TERMINOLOGY
Sequencer (Microprogram Sequencer)
A Microprogram Control Unit that determines
the Microinstruction Address to be executed
in the next clock cycle
- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping
MICROINSTRUCTION SEQUENCING
Sequencing Capabilities Required in a Control Storage
- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
Sequencing
Instruction code
Mapping
logic
Multiplexers
Control memory (ROM)
Subroutine
register
(SBR)
Branch
logic
Status
bits
Microoperations
Control address register
(CAR)
Incrementer
MUX
select
select a status
bit
Branch address
MAPPING OF INSTRUCTIONS
Sequencing
ADD Routine
AND Routine
LDA Routine
STA Routine
BUN Routine
Control
Storage
OP-codes of Instructions
ADD
AND
LDA
STA
BUN
Direct Mapping
Address
Mapping
Bits
10 xxxx 010
ADD Routine
Address
AND Routine
LDA Routine
STA Routine
BUN Routine
MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping function implemented by ROM or PLA
OP-code
Mapping memory
(ROM or PLA)
Control address register
Control Memory
Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram
1 0 1 1 Address
OP-code
Mapping bits
Microinstruction
address
0 x x x x 0 0
0 1 0 1 1 0 0
Machine
Instruction
Sequencing
MACHINE INSTRUCTION FORMAT
Microinstruction Format
Microprogram
EA is the effective address
Symbol OP-code Description
ADD 0000 AC ← AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC ← EA)
STORE 0010 M[EA] ← AC
EXCHANGE 0011 AC ← M[EA], M[EA] ← AC
Machine instruction format
I
Opcode
Address
Sample machine instructions
F1 F2 F3 CD BR AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F
F1 Microoperation Symbol
000 None NOP
001 AC ← AC + DR ADD
010 AC ← 0 CLRAC
011 AC ← AC + 1 INCAC
100 AC ← DR DRTAC
101 AR ← DR(0-10) DRTAR
110 AR ← PC PCTAR
111 M[AR] ← DR WRITE
Microprogram
F2 Microoperation Symbol
000 None NOP
001 AC ← AC - DR SUB
010 AC ← AC ∨ DR OR
011 AC ← AC ∧ DR AND
100 DR ← M[AR] READ
101 DR ← AC ACTDR
110 DR ← DR + 1 INCDR
111 DR(0-10) ← PC PCTDR
F3 Microoperation Symbol
000 None NOP
001 AC ← AC ⊕ DR XOR
010 AC ← AC’ COM
011 AC ← shl AC SHL
100 AC ← shr AC SHR
101 PC ← PC + 1 INCPC
110 PC ← AR ARTPC
111 Reserved
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.
Sample Format
five fields: label; micro-ops; CD; BR; AD
Label: may be empty or may specify a symbolic
address terminated with a colon
Micro-ops: consists of one, two, or three symbols
separated by commas
CD: one of {U, I, S, Z}, where U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
BR: one of {JMP, CALL, RET, MAP}
AD: one of {Symbolic address, NEXT, empty}
Microprogram
SYMBOLIC MICROPROGRAM - FETCH ROUTINE
AR ← PC
DR ← M[AR], PC ← PC + 1
AR ← DR(0-10), CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0
Symbolic microprogram for the fetch cycle:
ORG 64
PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
FETCH:
Binary equivalents translated by an assembler
Binary
address F1 F2 F3 CD BR AD
Microprogram
During FETCH, Read an instruction from memory
and decode the instruction and update PC
Sequence of microoperations in the fetch cycle:
This microprogram can be implemented using ROM
Microprogram
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
BRANCH 4 0000100 000 000 000 10 00 0000110
STORE 8 0001000 000 000 000 01 01 1000011
EXCHANGE 12 0001100 000 000 000 01 01 1000011
FETCH 64 1000000 110 000 000 00 00 1000001
INDRCT 67 1000011 000 100 000 00 00 1000100
BINARY MICROPROGRAM
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION -
Design of Control Unit
microoperation fields
3 x 8 decoder
F
3 x 8 decoder
F
3 x 8 decoder
F
Arithmetic
logic and
shift unit
AND
ADD
DRTAC
AC
Load
From
PC
From
DR(0-10)
Select
Multiplexers
AR
Load
Clock
AC
DR
DRTAR
PCTAR
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -
Design of Control Unit
Input
logic
I
0
I
1
T
MUX
Select
I
S
Z
Test
CD Field of CS
From
CPU
BR field
of CS
L(load SBR with PC)
for subroutine Call
S
0
S
1
for next address
selection
I
0
I
1
T Meaning Source of Address S
1
S
0
L
000 In-Line CAR+1 00 0
001 JMP CS(AD) 10 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 10 1
10x RET SBR 01 0
11x MAP DR(11-14) 11 0
L
S
= I
S
= I
I
- I
’T
L = I
’I
T
Input Logic
MICROPROGRAM SEQUENCER
Design of Control Unit
S
1 MUX
External
(MAP)
SBR
Load
Incrementer
CAR
Input
logic
I
0
T
MUX
Select
I
S
Z
Test
Clock
Control memory
Microops CD BR AD
L
I
1
S
0
......