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Multiprocessors - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

Chhattisgarh Swami Vivekanand Technical UniversityComputer Architecture and Organization

Multiprocessors, Characteristics of Multiprocessors, Interconnection Structures, Interprocessor Arbitration, Interprocessor Communication, Synchronization, Cache Coherence are key points of this lecture.

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Multiprocessors
Computer Organization Computer Architectures Lab
MULTIPROCESSORS
• Characteristics of Multiprocessors
• Interconnection Structures
• Interprocessor Arbitration
• Interprocessor Communication
and Synchronization
• Cache Coherence
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MULTIPROCESSORS

  • Characteristics of Multiprocessors
  • Interconnection Structures
  • Interprocessor Arbitration
  • Interprocessor Communication

and Synchronization

  • Cache Coherence

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TERMINOLOGY

Parallel Computing

Simultaneous use of multiple processors, all components of a single architecture, to solve a task. Typically processors identical, single user (even if machine multiuser)

Distributed Computing

Use of a network of processors, each capable of being viewed as a computer in its own right, to solve a problem. Processors may be heterogeneous, multiuser, usually individual task is assigned to a single processors

Concurrent Computing

All of the above?

Characteristics of Multiprocessors

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SPEEDUP AND EFFICIENCY

A: Given problem

T*(n): Time of best sequential algorithm to solve an instance of A of size n on 1 processor Tp(n): Time needed by a given parallel algorithm and given parallel architecture to solve an instance of A of size n, using p processors

Note: T*(n) ≤ T 1 (n)

Speedup: T*(n) / Tp(n)

Efficiency: T*(n) / [pTp(n)]

Speedup should be between 0 and p, and Efficiency should be between 0 and 1 Speedup is linear if there is a constant c > 0 so that speedup is always at least cp.

1 2 3 4 5 6 7 8 9 10 Processors

Speedup Perfect Speedup

Characteristics of Multiprocessors

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AMDAHL’S LAW

Given a program f : Fraction of time that represents operations that must be performed serially

Maximum Possible Speedup: S

S ≤ , with p processors f + (1 - f ) / p

S < 1 / f , with unlimited number of processors

  • Ignores possibility of new algorithm, with much smaller f
  • Ignores possibility that more of program is run from higher speed memory such as Registers, Cache, Main Memory
  • Often problem is scaled with number of processors, and f is a function of size which may be decreasing (Serial code may take constant amount of time, independent of size)

Characteristics of Multiprocessors

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Tightly Coupled System

  • Tasks and/or processors communicate in a highly synchronized fashion
  • Communicates through a common shared memory
  • Shared memory system

Loosely Coupled System

  • Tasks or processors do not communicate in a synchronized fashion
  • Communicates by message passing packets
  • Overhead for data exchange is high
  • Distributed memory system

COUPLING OF PROCESSORS

Characteristics of Multiprocessors

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Granularity of Parallelism

GRANULARITY OF PARALLELISM

Coarse-grain

  • A task is broken into a handful of pieces, each of which is executed by a powerful processor
  • Processors may be heterogeneous
  • Computation/communication ratio is very high

Medium-grain

  • Tens to few thousands of pieces
  • Processors typically run the same code
  • Computation/communication ratio is often hundreds or more

Fine-grain

  • Thousands to perhaps millions of small pieces, executed by very small, simple processors or through pipelines
  • Processors typically have instructions broadcasted to them
  • Compute/communicate ratio often near unity

Characteristics of Multiprocessors

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SHARED MEMORY MULTIPROCESSORS

Characteristics

All processors have equally direct access to one large memory address space

Example systems

  • Bus and cache-based systems: Sequent Balance, Encore Multimax
  • Multistage IN-based systems: Ultracomputer, Butterfly, RP3, HEP
  • Crossbar switch-based systems: C.mmp, Alliant FX/

Limitations

Memory access latency; Hot spot problem

Interconnection Network

...

P P... P

M (^) M M

Buses, Multistage IN, Crossbar Switch

Characteristics of Multiprocessors

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MESSAGE-PASSING MULTIPROCESSORS

Characteristics

  • Interconnected computers
  • Each processor has its own memory, and communicate via message-passing

Example systems

  • Tree structure: Teradata, DADO
  • Mesh-connected: Rediflow, Series 2010, J-Machine
  • Hypercube: Cosmic Cube, iPSC, NCUBE, FPS T Series, Mark III

Limitations

  • Communication overhead; Hard to programming

Message-Passing Network

P P... P

M (^) M... M

Point-to-point connections

Characteristics of Multiprocessors

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  • A collection of signal lines that carry module-to-module communication
  • Data highways connecting several digital system elements

Operations of Bus

Bus

M3 wishes to communicate with S

[1] M3 sends signals (address) on the bus that causes S5 to respond [2] M3 sends data to S5 or S5 sends data to M3(determined by the command line)

Master Device: Device that initiates and controls the communication

Slave Device: Responding device

Multiple-master buses -> Bus conflict -> need bus arbitration

Devices M3 S7 M6 S5 M4 S

BUS

Interconnection Structure

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SYSTEM BUS STRUCTURE FOR MULTIPROCESSORS

Interconnection Structure

Common Shared Memory

System Bus Controller

CPU IOP^ MemoryLocal

System Bus Controller

CPU (^) MemoryLocal

System Bus Controller

CPU IOP^ MemoryLocal

Local Bus

SYSTEM BUS

Local Bus Local Bus

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CROSSBAR SWITCH

Interconnection Structure

MM

CPU

CPU

CPU

CPU

Memory modules MM2 MM3 MM

Block Diagram of Crossbar Switch

Memory Module

data address R/W memory enable

data,address, and control from CPU 1

data,address, and control from CPU 2

data,address, and control from CPU 3

data,address, and control from CPU 4

Multiplexers and arbitration logic

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MULTISTAGE SWITCHING NETWORK

Interconnection Structure

A

B

0

1

A connected to 0

A

B

0

1

A connected to 1

A

B

0

1

B connected to 0

A

B

0

1

B connected to 1

Interstage Switch

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HYPERCUBE INTERCONNECTION

Interconnection Structure

  • p = 2 n
  • processors are conceptually on the corners of a n-dimensional hypercube, and each is directly connected to the n neighboring nodes
  • Degree = n

One-cube Two-cube Three-cube

(^00111)

(^1 00 )

010 110

(^011 )

101

100

001

000

n-dimensional hypercube (binary n-cube)

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INTERPROCESSOR ARBITRATION

Bus Board level bus Backplane level bus Interface level bus

System Bus - A Backplane level bus

  • Printed Circuit Board
  • Connects CPU, IOP, and Memory
  • Each of CPU, IOP, and Memory board can be plugged into a slot in the backplane(system bus)
  • Bus signals are grouped into 3 groups

Data, Address, and Control(plus power)

  • Only one of CPU, IOP, and Memory can be granted to use the bus at a time
  • Arbitration mechanism is needed to handle multiple requests

Interprocessor Arbitration

e.g. IEEE standard 796 bus

  • 86 lines Data: 16(multiple of 8) Address: 24 Control: 26 Power: 20

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