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Sequential Circuits
We have spent some time considering combinational circuits. We now consider sequential circuits; that is, circuits with memory. Feedback is one specific type of memory. By feedback we mean applying the output of a circuit back to its input. We compare the two types of circuits. Combinational Circuits Sequential Circuits No Memory Memory No flip-flops, Flip-flops may be used only combinational gates Combinational gates may be used No feedback Feedback is allowed Output for a given set of The order of input change Inputs is independent of is quite important and may order in which these inputs produce significant differences were changed, after the in the output. output stabilizes. The following figure shows a way to consider sequential circuits. The input is fed into the combinational logic (AND gates, OR gates, and NOT gates). The output of the combinational logic is fed into the memory and available as input to the combinational logic on the next tick of the clock. The clock input is very important to the concept of a sequential circuit. At each “tick” of the clock the output of a sequential circuit is determined by its input and by its state. By Q(T) we denote the state of a sequential circuit at time T – this is basically its memory. We watch the state of the circuit change from Q(T) to Q(T + 1) as the clock ticks.
We have two topics about sequential circuits to be covered in this section:
- Analysis of sequential circuits
- Design (synthesis) of sequential circuits Circuit analysis begins with a circuit diagram or a black box and ends with an identification of the sequential circuit implemented by the device – normally a truth table. The steps are:
- Identify the inputs and the outputs
- Express each output as a Boolean function of the inputs and the present state Q(T)
- Identify the circuit if possible. Circuit design begins with a complete description of the circuit and ends with a design. There are two types of sequential circuits – synchronous and asynchronous. Asynchronous circuits do not have a common clock; they are faster and harder to design. As should be inferred from the previous discussion we shall focus on synchronous circuits. The basic building blocks of synchronous circuits are flip-flops , which should be considered as single bit memory elements: each flip-flop can store either a 0 or a 1. Flip-flops have inputs, outputs, and state Q(T); Q(T) = 0 or Q(T) = 1. The outputs of a flip-flop at any given time are the present state and its complement: Q(T) and Q’(T). There are two standard ways to describe a flip-flop: the characteristic table and the excitation table. A characteristic table is a truth table that determines the next state of the flip-flop in terms of the input and present state. An excitation table specifies the input required to produce a desired next state at Q(T + 1) given the present state at Q(T). There are four basic types of flip-flops: SR, JK, D, and T. We shall specify each flip-flop by the characteristic and excitation tables and ignore the details of its construction. The SR flip-flop has two inputs S and R. The clock input is always present and shown here just to be complete. We first give the characteristic table as a truth table. S R Q(T + 1) 0 0 Q(T) 0 1 0 1 0 1 1 1 Not allowed – error The excitation table for the flip-flop is shown at Q(T) Q(T + 1) S R the right. Note that the table shows what 0 0 0 d inputs are required to get the desired next 0 1 1 0 state given the existing present state. 1 0 0 1 NOTE: We have some new terminology 1 1 d 0 to explain. Q Q’ S R Clock
The T flip-flop maintains its state for Q = 0 and complements the state for Q = 1. Again, the characteristic and excitation tables for this flip-flop are quite simple T Q(T + 1) Q(T) Q(T + 1) T 0 Q(T) 0 0 0 1 Q’(T) 0 1 1 1 0 1 1 1 0 As an aside, we note that a JK flip-flop can be used to synthesize both a D and a T flip-flop. Master-Slave Flip-Flop There are times in digital design where it is desirable to change the input of a flip-flop without immediately affecting its output. In such situations a Master-Slave configuration, comprising two flip-flops, is one of the preferred solutions. Here is a Master-Slave flip-flop built from a JK and an SR flip-flop. Note that the inputs to the SR flip-flop are never 1 1. When the clock signal goes high, the master flip-flop accepts input and the slave flip-flop is inactive. When the clock signal goes low, the master flip-flop becomes inactive and the slave flip-flop accepts its input and possibly changes its state. We normally draw this as one flip-flop. Political Correctness Note: There have been many contests to suggest a different name for this arrangement of flip-flops. So far, all suggestions have been silly. Analysis of Sequential Circuits We first study the analysis of digital circuits, then we study the design. There are a number of steps in the analysis of a circuit. Where to begin depends on what one has. When given a circuit diagram, the following steps are used to begin the analysis.
- Determine the inputs and outputs of the circuit. Assign variables to represent these.
- Determine the inputs and outputs of the flip-flops
- Construct the Next State and Output tables, translate these to the State Diagram.
- If possible, identify the circuit. There are no good rules for this step. Consider the following circuit, taken from Figure 2.18 on page 94 of the textbook.
T
Clock
Q
Q’
We use the following variables in the analysis of this circuit with a single flip-flop. X denotes the input, Y denotes the output of the flip-flop (Y’ also), and Z the output of the circuit. The first step is to determine the equations for Z, the output, and D, the input to the flip-flop. By inspection, we determine the following for the equations: Z = X Y’ + X’ Y D = X + Y Noting that Q = Y (the state of a flip-flop is also its output) we construct the following Next- State diagram for the flip-flop, based on the characteristic table of a D flip-flop. X Q(T) D Q(T + 1) 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 The output table is similarly constructed X Q(T) Z 0 0 0 0 1 1 1 0 1 1 1 0 These two tables are combined to form the transition table. X Q(T) Q(T + 1) / Z 0 0 0 / 0 0 1 1 / 1 1 0 1 / 1 1 1 1 / 0
Design of Sequential Circuits Having seen how to analyze digital circuits, we now investigate how to design digital circuits. We assume that we are given a complete and unambiguous description of the circuit to be designed as a starting point. At this level, most design problems focus on one of two topics: modulo-N counters and sequence detectors. A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a target sequence has been detected. There are two basic types: overlap and non-overlap. In an sequence detector that allows overlap, the final bits of one sequence can be the start of another sequence. Our example will be a 11011 sequence detector. It raises an output of 1 when the last 5 binary bits received are 11011. At this point, a detector with overlap will allow the last two 1 bits to serve at the first of a next sequence. By example we show the difference between the two detectors. Suppose an input string 11011011011. 11011 detector with overlap X 11011011011 Z 00001001001 11011 detector with no overlap Z 00001000001 The sequence detector with no overlap allowed resets itself to the start state when the sequence has been detected. Write the input sequence as 11011 011011. After the initial sequence 11011 has been detected, the detector with no overlap resets and starts searching for the initial 1 of the next sequence. The detector with overlap allowed begins with the final 11 of the previous sequence as ready to be applied as the first 11 of the next sequence; the next bit it is looking for is the 0. Here is an overview of the design procedure for a sequential circuit.
- Derive the state diagram and state table for the circuit.
- Count the number of states in the state diagram (call it N) and calculate the number of flip-flops needed (call it P) by solving the equation 2 P-1^ < N 2 P. This is best solved by guessing the value of P.
- Assign a unique P-bit binary number (state vector) to each state. Often, the first state = 0, the next state = 1, etc.
- Derive the state transition table and the output table.
- Separate the state transition table into P tables, one for each flip-flop. WARNING: Things can get messy here; neatness counts.
- Decide on the types of flip-flops to use. When in doubt, use all JK’s.
- Derive the input table for each flip-flop using the excitation tables for the type.
- Derive the input equations for each flip-flop based as functions of the input and current state of all flip-flops.
- Summarize the equations by writing them in one place.
- Draw the circuit diagram. Most homework assignments will not go this far, as the circuit diagrams are hard to draw neatly. We now do the 11011 sequence detector as an example. We shall break some of the above big steps into sub-steps to make things easier. We begin with the formal problem statement.
Problem: Design a 11011 sequence detector using JK flip-flops. Allow overlap. Step 1 – Derive the State Diagram and State Table for the Problem The method to be used for deriving the state diagram depends on the problem. I show the method for a sequence detector. At this point in the problem, the states are usually labeled by a letter, with the initial state being labeled “A”, etc. Step 1a – Determine the Number of States It can be proven that an N-bit sequence detector requires at least N states to function correctly. It can also be shown that a circuit with more than N states is unnecessarily complicated and a waste of hardware; thus, an N-bit sequence detector has N states. We are designing a sequence detector for a 5-bit sequence, so we need 5 states. We label these states A, B, C, D, and E. State A is the initial state. Step 1b – Characterize Each State by What has been Input and What is Expected State Has Awaiting A -- 11011 B 1 1011 C 11 011 D 110 11 E 1101 1 Step 1c – Do the Transitions for the Expected Sequence Here is a partial drawing of the state diagram. It has only the sequence expected. Note that the diagram returns to state C after a successful detection; the final 11 are used again. Note the labeling of the transitions: X / Z. Thus the expected transition from A to B has an input of 1 and an output of 0. The transition from E to C has an output of 1 denoting that the desired sequence has been detected.
B
C
E
A
D
Step 2 – Determine the Number of Flip-Flops Required We have 5 states, so N = 5. We solve the equation 2P-1^ < 5 2 P^ by inspection, noting that it is solved by P = 3. So we need three flip-flops. Step 3 – Assign a unique P-bit binary number (state vector) to each state. The simplest way is to make the following assignments A = 000 B = 001 C = 010 D = 011 E = 100 Occasionally, a better assignment can be detected by inspection of the next state table. I note that the next states in the table cluster into two disjoint sets for X = 0 and X = 1. For X = 0 the possible next states are A and D For X = 1 the possible next states are B, C, and E. For this reason, I elect to give even number assignments to states A and D, and to give odd number assignments to states B, C, and E. Being somewhat traditional, I want to assign the state numbers in increasing order so that we don’t get totally confused. The assignment is A = 000 B = 001 C = 011 Note that states 010, 110, and 111 are not used. D = 100 E = 101 Step 4 – Generate the Transition Table With Output Note that in many designs, such as counters, the states are already labeled with binary numbers, so the state table is the transition table. We shall label the internal state by the three bit binary number Y 2 Y 1 Y 0 and use the three-bit vectors defined above. Present State Next State / Output X = 0 X = 1
Y 2 Y 1 Y 0 Y 2 Y 1 Y 0 / Z Y 2 Y 1 Y 0 / Z
A 0 0 0 0 0 0 / 0 0 0 1 / 0
B 0 0 1 0 0 0 / 0 0 1 1 / 0
C 0 1 1 1 0 0 / 0 0 1 1 / 0
D 1 0 0 0 0 0 / 0 1 0 1 / 0
E 1 0 1 0 0 0 / 0 0 1 1 / 1
Step 4a – Generate the Output Table and Equation The output table is generated by copying from the table just completed. The output equation can be obtained from inspection. As is the case with most sequence detectors, the output Z is 1 for only one combination of present state and input. Thus we get Z = X Y 2 Y 1 ’ Y 0. This can be simplified by noting that the state 111 does not occur, so the answer is Z = X Y 2 Y 0. Step 5 – Separate the Transition Table into Three Tables, One for Each Flip-Flop We shall generate a present state / next state table for each of the three flip-flops; labeled Y 2 , Y 1 , and Y 0. It is important to note that each of the tables must include the complete present state, labeled by the three bit vector Y 2 Y 1 Y 0. Y2 Y1 Y PS Next State PS Next State PS Next State Y 2 Y 1 Y 0 X = 0 X = 1 Y 2 Y 1 Y 0 X = 0 X = 1 Y 2 Y 1 Y 0 X = 0 X = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 Match Y 1 Y 2 Y 0 ’ 0 Y 0 0 1 Before trying step 6, I shall note a quick, but often messy, implementation. We look at an implementation using D flip-flops only. For each flip-flop, we have the desired next state for each combination of present state and input. Remember that the D flip-flop equation is D = Q(T + 1); i.e., input to the flip-flop whatever the next state is to be. Thus, this design is D 2 = X’Y 1 + XY 2 Y 0 ’ D 1 = X Y 0 D 0 = X While this may be an acceptable implementation, it is important to complete the original design problem using JK flip-flops. What we want is input equations for J 2 , K 2 , J 1 , K 1 , J 0 , and K 0. Inspection of the above gives little clue for the first two flip-flops, but any student recalling the use of a JK flip-flop to implement a D flip-flop will see immediately that the input equation for flip-flop 0 is J 0 = X and K 0 = X’. Step 6 – Decide on the type of flip-flops to be used. The problem stipulates JK flip-flops, so we use them. As an aside, we examine the difficulties of designing the circuit with D flip-flops. Present State X = 0 X = 1
Y 2 Y 1 Y 0 0 0
We now derive the input equations for flip-flop 1. The patterns are detected first for X = 0 and X = 1 separately and then combined. X = 0 X = 1 J 1 = 0 J 1 = Y 0 K 1 = 1 K 1 = 0 thus J 1 = XY 0 and K 1 = X’. We now derive the input equations for flip-flop 0. The patterns are detected as above X = 0 X = 1 J 0 = 0 J 0 = 1 K 0 = 1 K 0 = 0 thus J 0 = X and K 0 = X’, as expected. Step 9 – Summarize the Equations Z = XY 2 Y 0 J 2 = X’Y 1 and K 2 = X’ + Y 0 J 1 = XY 0 and K 1 = X’ J 0 = X and K 0 = X’ Step 10 – Draw the Circuit I usually do not ask for this step as it tends to be messy and is always hard to grade. The figure on the next page has been added to show a typical drawing of this circuit as implemented by JK flip-flops.
Y 2 Y 1 Y 0 X = 0 X = 1
Y 1 J 1 K 1 Y 1 J 1 K 1
0 0 0 0 0 d 0 0 d 0 0 1 0 0 d 1 1 d 0 1 1 0 d 1 1 d 0 1 0 0 0 0 d 0 0 d 1 0 1 0 0 d 1 1 d Y 2 Y 1 Y 0 X = 0 X = 1 Y 0 J 0 K 0 Y 0 J 0 K 0 0 0 0 0 0 d 1 1 d 0 0 1 0 d 1 1 d 0 0 1 1 0 d 1 1 d 0 1 0 0 0 0 d 1 1 d 1 0 1 0 d 1 1 d 0
Here is the circuit for the 11011 sequence detector as implemented with JK flip-flops. The equations implemented in this design are: Z = XY 2 Y 0 J 2 = X’Y 1 K 2 = X’ + Y 0 J 1 = XY 0 K 1 = X’ J 0 = X K 0 = X’ Here is the same design implemented with D flip-flops. The equations for this design are D 2 = X’Y 1 + XY 2 Y 0 ’ D 1 = X Y 0 D 0 = X
More on Overlap – What it is and What it is not At this point, we need to focus more precisely on the idea of overlap in a sequence detector. For an extended example here, we shall use a 1011 sequence detector. The next figure shows a partial state diagram for the sequence detector. The final transitions from state D are not specified; this is intentional. Here we focus on state C and the X= transition coming out of state D. By definition of the system states, State C – the last two bits were 10 State D – the last three bits were 101. If the system is in state D and gets a 0 then the last four bits were 1010, not the desired sequence. If the last four bits were 1010, the last two were 10 – go to state C. The design must reuse as many bits as possible. Note that this decision to go to state C when given a 0 is state D is totally independent of whether or not we are allowing overlap. The question of overlap concerns what to do when the sequence is detected , not what to do when we have input that breaks the sequence. Just to be complete, we give the state diagrams for the two implementations of the sequence detector – one allowing overlap and one not allowing overlap. The student should note that the decision on overlap does not affect designs for handling partial results – only what to do when the final 1 in the sequence 1011 is detected.
A Word About Counters and Numbering their States For this example, we consider modulo-4 counters, both up-counters and down-counters. Modulo-4 up-counters count 0, 1, 2, 3, 0, 1, 2, 3, 0, etc. Modulo-4 down-counters count 0, 3, 2, 1, 0, 3, 2, 1, 0, etc. Sequence detectors, such as that just studied, have input – specifically representing the stream of bits to be detected. Pure counters do not have input; specifically neither an up-counter nor a down-counter has input. An up-down counter does have a single input, denoted as X, indicating the direction in which to count. Here are the state diagram and state table of a modulo-4 down counter. The state table shows the present state and next state. PS NS PS = Present State 0 3 NS = Next State 1 0 2 1 3 2 In this, and all counters the association of state vectors to the states is forced: 0 = 00, 1 = 01, 2 = 10, 3 = 11. Any other assignment yields a different counter. Here are the state diagram and state table of a modulo-4 up-down counter Here, the state table depends on X – the input used to specify the counting direction. PS Next State X = 0 X = 1 0 1 3 1 2 0 2 3 1 3 0 2 Again, the assignment of binary numbers follows a fixed and specific pattern. BOTTOM LINE: In a counter, states are named by the number they represent. In any modulo-4 counter, the states are named 0, 1, 2, and 3. The assignment of binary numbers or vectors to the states must follow a fixed rule – give the state a binary number corresponding to its representation as an unsigned binary number. For a modulo-4 counter, these assignments must be as follows: 0 = 00 1 = 01 2 = 10 3 = 11. Any other assignment yields a different counter design.
The table at right is the state table, with the state number and alias given for both the present and next state. We keep the alias for convenience only as we have not resolved the duplicate “RR” alias. At this point, we note that we have six states and are ready for Step 2: Count the Flip-Flops. We need to use three flip-flops; P = 3. Step 3: Assign a Binary Number to Each State The solution here is obvious – we treat each number as a three-bit unsigned integer and assign the binary numbers 000, 001, 010, 011, 100, and 101. At this point, we have two binary patterns that are not assigned 110 (state 6) and 111 (state 7). Although these states are supposedly unreachable in our design, I propose to handle them anyway as we are designing a device that is safety-critical. This design specifies that the next state following either state 6 or state 7 will be state 0. As a safety consideration, we further specify that both states 6 and state 7 display Red on each of the two lights as we consider these to be failure states. Following our standard design practice, we label the flip-flops with the integers 2, 1, and 0, and call the outputs of the flip-flops Q 2 , Q 1 , and Q 0 , as Y is taken to stand for Yellow. Step 4: Derive the State Transition Table and Output Table. The first step in deriving the output table is to define the output. The design calls for two coupled traffic lights, each with the standard colors Red, Green, and Yellow. The circuit will thus have six outputs R1, G1, Y1, R2, G2, and Y2 – the first three outputs to light 1 and the second three outputs to light 2. The output table is somewhat complicated. It may seem that we have six signals to generate based on the three binary values Y 2 , Y 1 , and Y 0 , but we take a short-cut. We note that each light is either Red, Green, or Yellow, and when it is not either Green or Yellow it must be Red. Thus, the only signals we generate directly are G1, Y1, G2, and Y2. Here are the output equations G1 = Q 2 Q 1 ’Q 0 ’ G2 = Q 2 ’Q 1 ’Q 0 Y1 = Q 2 Q 1 ’Q 0 Y2 = Q 2 ’Q 1 Q 0 ’ R1 = (G1 + Y1)’ R2 = (G2 + Y2)’ Present State Next State Number Alias Number Alias 0 RR 1 RG 1 RG 2 RY 2 RY 3 RR 3 RR 4 GR 4 GR 5 YR 5 YR 0 RR Alias Q 2 Q 1 Q 0 R1 G1 Y1 R2 G2 Y 0 RR 0 0 0 1 0 0 1 0 0 1 RG 0 0 1 1 0 0 0 1 0 2 RY 0 1 0 1 0 0 0 0 1 3 RR 0 1 1 1 0 0 1 0 0 4 GR 1 0 0 0 1 0 1 0 0 5 YR 1 0 1 0 0 1 1 0 0 6 RR 1 1 0 1 0 0 1 0 0 7 RR 1 1 1 1 0 0 1 0 0
If we wanted to provide extra fault tolerance, we would demand that when one light is either green or yellow, the other must be red, thus generating the equations R1 = (G1 + Y1)’ + G2 + Y2 and R2 = (G2 + Y2)’ + G1 + Y A bit of reflection will show that, even with this design, it is possible for one light to show more than one color. Here we assume a person seeing both red and green on a traffic light would assume something is very wrong. We now consider the state transition table expressed in terms of Q 2 , Q 1 , and Q 0. Before breaking this into three tables, one for each flip-flop, we note the handling of the supposedly non-reachable states 6 and 7. The design here is based on fault tolerance , the idea that the circuit should have some ability to restore itself from faulty operation. Admittedly, the strategy reflected in this design may not be realistic. It is shown mostly to draw the student’s attention to the concepts and not to present an optimal solution. Step 5: Separate the Table into Three Tables, One for Each Flip-Flop Remember that each table must have a complete description of the present state. Q 2 Q 1 Q 0 PS NS PS NS PS NS Q 2 Q 1 Q 0 Q 2 Q 2 Q 1 Q 0 Q 1 Q 2 Q 1 Q 0 Q 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 2 0 1 0 0 1 1 3 0 1 1 1 0 0 4 1 0 0 1 0 1 5 1 0 1 0 0 0 6 1 1 0 0 0 0 7 1 1 1 0 0 0
