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CPSC 440 Lecture 4
The Processor: Datapath and Control
What will be implemented?
- Data transfer: lw, sw
- R-type: add, sub, and, or, slt
- Branch: beq and jump j
An abstract view (excluding branch)
See Fig. 4.1 on page 302.
Adding multiplexes and control lines
See Fig. 4.2 on page 304.
In more details
See Fig. 4.5 – 4.
R-type
See Fig. 4.10 on page 314.
Data transfer ( lw, sw) and branch instruction
See Fig. 4.11 on page 315.
Adding multiplexes and control lines
See Fig. 4.15 on page 320.
A simple schema
See Fig. 4.17 on page 322.
Note: you need to know what type of instructions will go through which part of the circuit.
Designing the Main Control Unit
See Fig. 4.18 on page 323.
Note: you need to know how to come up with the table by looking at the datapath (except for the ALUOp’s).
Implementing jumps
See Fig. 4.24 on page 329.
Breaking the Instruction Execution into five steps
- IF: fetch instruction from memory.
- ID: read registers while decoding the instruction.
- EX: execute the operation or calculate an address.
- MEM: access an operand in data memory.
- WB: Write the result into a register.
See Fig. 4.33 on page 345.
An Overview of Pipelining
Instruction\Time 0 1 2 3 4 5 6 7 8 Instruction1 IF ID EX MEM WB Instruction2 IF ID EX MEM WB Instruction3 IF ID EX MEM WB Instruction4 IF ID EX MEM WB Instruction5 IF ID EX MEM WB
Performance: No pipelining: 5xN With pipelining: N + 4
More hardware is needed. See Fig. 4.35 on page 347.
Data hazard
sub $2, $1, $ and $12, $2, $ or $13, $6, $ add $14, $2, $ sw $15, 100($2)
Without forwarding Fig. 4.52 on page 364 With forwarding Fig. 4.53 on page 367 Also see Fig. 4.54 on page 368
Example: addi $s0, $zero, 400 Loop: lw $t1, 0($s0) addi $t2, $t1, 100 sw $t2, 0($s0) addi $s0, $s0, - bne $s0, $zero, Loop
Question: can forwarding solve all data hazards? Answer: except for the load-use stall.
load-use hazard lw $2, 20($1) and $4, $2, $
