Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
A set of lecture notes for cs 333, focusing on pipelining and instruction execution. It covers key concepts such as pipelining, throughput, latency, speedup, structural hazards, data hazards, and control hazards. The notes also discuss various solutions to hazards, including bypassing, pipeline scheduling, and delayed branches.
Typology: Study notes
1 / 45
This page cannot be seen from the preview
Don't miss anything!
2008-1-
St
t^
l h
d
Structural hazardsData hazardsControl hazards Exceptions (Section A.4)Multicycle operations (Section A.5)
2008-1-
time
time
1/Throughput
1/Throughput
instrns
instrns
g p
Ideally
Time Latency
Latency
Time
sequential
Pipeline Depth
Time
pipeline
Time
sequential
d^
l^
h
sequential Time
pipeline
Speedup =
= Pipeline Depth
2008-1-
Let
0 be extra delay per stage e.g., latches Δ^
limits the useful depth of a pipeline. With an n-stage pipelineWith an n stage pipeline
Throughput =
i
g p
Latency = n
)^ i
i
i
Speedup =
2008-1-
Let
t^ 1,2,
ns and
ns
Throughput =Latency =Speedup =
2008-1-
MIPS ISAOnly loads and stores affect memory
Base register + immediate offset = effective address ALU operations
Only access registersTwo sources – two registers, or register and immediate Branches and jumps
Comparison between a register and zeroAdd
ff
Address = PC + offset
2008-1-
Pipeline Stages
IF – Instruction FetchID
Instruction decode register read branch computation ID – Instruction decode, register read, branch computationEX – Execution and Effective AddressMEM – Memory AccessWB – Writeback
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
i^
IF
ID
EX
MEM WB
i+
IF
ID
EX
MEM WB
i+
IF
ID
EX
MEM WB
i+
IF
ID
EX
MEM WB
i+
IF
ID
EX
MEM WB
i+
IF
ID
EX MEM WB
Pipelining really isn
't this simple
Pipelining really isn t this simple
2008-1-
HazardsStructural HazardsData HazardsControl Hazards
2008-1-
Pipeline interlock logic
Detects hazard and takes appropriate action Simplest solution: stall
Increases CPIDecreases performance Other solutions are harder, but have better performance
2008-1-
Pipeline Resource
Often complex to doUse when simple to doE.g., write & read registers every cycle
Structural hazards are avoided if each instruction uses a resource
At most onceAl
i^
h^
i^
li
Always in the same pipeline stageFor one cycle(^
l^
h^
t^
i^
t^
ti^
th
no cycle where two instructions use the same resource)
2008-1-
Loads/stores (MEM) use same memory port as instrn fetches (IF)30% of all instructions are loads and storesAssume
old
is 1.
1
2
3
4
5
6
7
8
9
i^
IF
ID
EX
MEM WB
l^
d
i^
IF
ID
EX
MEM WB
<— a load
i+
IF
ID
EX
MEM WB
i+
IF
ID
EX
MEM WB
i+
**
IF
ID
EX
MEM WB
i+
IF
ID
EX MEM WB
How much faster could a new machine with two memory ports be?How
much faster could a new machine with two memory ports be?
2008-1-
r^
ritten
ADD r1,,
IF^
ID^
EX
MEM
WBNOT OK! r1 written
SUB , r1,
IF^
ID^
EX
MEM
WB
r1 read
r1 written
LW r1,,
IF^
ID^
EX
MEM
WBNOT OK!
SUB
1
IF^
ID^
EX
MEM
WB
r1 read
memory written
SUB , r1,
IF^
ID^
EX
MEM
WB
SW r1,100(r0)
IF^
ID^
EX
MEM
WBCORRECT!
LW r2,100(r0)
IF^
ID^
EX
MEM
WB
memory read
(Unless LW instrn is at address 100(r0))
2008-1-
Solutions must first detect RAW, and then ...Stall ADD r1,,
IF^
ID^
EX
MEM
WB r1 written
SUB , r1,
IF^
ID^
stall
stall
EX
MEM
WB
r1 read
(Assumes registers written then read each cycle)
i^
l
Increases CPI (plus 2 per stall in 5 stage pipeline)U^
f^
t
Use for rare events
2008-1-
Figure A.
g
Additional hardware
Muxes supply correct result to ALU Additi
l^
t^
l
Additional control
Interlock logic must control muxes
2008-1-
Hybrid solution sometimes required:LW^
r1,, IF
ID^
EX
MEM
WB
r1 written
data available
SUB , r1,
IF^
ID^
stall
EX
MEM
WB
r1 read
data used
One-cycle bubble if result of load used by next instructionPi
li^
h d li
il^
i
Pipeline scheduling at compile-time
Moves instructions to eliminate stalls
