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Advanced RISC Machines
ARM
Document Number: ARM DDI 0035A Issued: January 1996 Copyright Advanced RISC Machines Ltd (ARM) 1996 All rights reserved
ARM 7100
Preliminary Data Sheet
Preliminary
Proprietary Notice
ARM and the ARM Powered logo are trademarks of Advanced RISC Machines Ltd.
SPI is a registered trademark of Motorola. Microwire is a registered trademark of National Semiconductor.
Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this datasheet is subject to continuous developments and improvements. All particulars of the product and its use contained in this datasheet are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded.
This datasheet is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this datasheet, or any error or omission in such information, or any incorrect use of the product.
Change Log
Issue Date By Change
-01 Jan 95 AW Created -02 Feb 95 AW Changes after an initial preliminary review. Changes to reflect updated specification. A draft1 Dec 95 AP Changes to reflect updated specification. A Jan 96 AP Minor edits; addition of timing diagrams.
Preliminary
Preface
Preface-ii
ARM7100 Data Sheet
The ARM7100 is a high integration microcontroller particularly well-suited for PDAs, smart mobile phones, handheld games, portable instruments and similar applications. Built around the ARM microprocessor, the ARM7100 integrates LCD control, glueless DRAM interface, UART with infra-red SIR protocol support and the other peripherals required for handheld computing applications. In normal operation at 18.4MHz at 3.3V, the ARM7100 consumes an extremely low 70mW and in standby, less than 40μW, which gives excellent battery performance. System power is minimized by the ability to use self-refresh DRAM when in standby. ARM7100 was implemented using a modular design methodology and the AMBA internal bus architecture. The ARM7100 is the ideal starting point from which to consider further ASSP devices for volume OEM applications.
Applications
High integration and low power consumption makes the ARM7100 ideal for battery-powered portable computing applications: l PDAs l Smart Mobile phones l Handheld games l Electronic books and organizers l Handheld instruments and data collection devices l High specification pagers l Mobile epos terminals Its high performance and low cost features make the ARM7100 also suitable for: l Office automation (photocopiers, faxes) l Automotive user consoles
Features
l 32-bit ARM710 RISC cached processor l 8Kb cache, memory management unit and write buffer to deliver strong performance with inexpensive memory l Very low chip and system power consumption (two low power modes and advanced power management) l Glueless DRAM interface, which supports self-refresh DRAM to further reduce system power consumption l 3072Mb total physical address range l Support for 8-bit, 16-bit or 32-bit wide ROM/SRAM devices l 36 bits of general purpose I/O l Flexible LCD controller with DMA support l Full duplex UART with two 16-byte FIFOs and IrDA industry standard infra-red protocol support l Synchronous serial interface supporting multiple protocols for peripheral expansion l Telephony CODEC interface l Other peripherals include timer/counters, real-time clock, DC-DC converter interface and on-chip clock generators
Contents
ARM7100 Data Sheet Contents-ii
Contents ARM7100 Data Sheet Contents-iii
- 1 Introduction 1- Preliminary
- 1.1 Introduction 1-
- 1.2 System Description 1-
- 1.3 Block Diagram 1-
- 1.4 CPU Core 1-
- 1.5 Datasheet Notation 1-
- 2 Signal Description 2-
- 2.1 Signal Descriptions 2-
- 3 The ARM Processor Macrocell 3-
- 3.1 Introduction 3-
- 3.2 Instruction set 3-
- 3.3 Memory Interface 3-
- 3.4 Clocking 3-
- 3.5 ARM Processor Block Diagram 3-
- 4 The ARM Processor Programmer's Model 4-
- 4.1 Introduction 4-
- 4.2 Register Configuration 4-
- 4.3 Operating Mode Selection 4-
- 4.4 Registers 4-
- 4.5 Exceptions 4-
- 4.6 Configuration Control Registers 4-
- 4.7 Reset 4-
- 5 ARM Processor Instruction Set 5-
- 5.1 Instruction Set Summary 5-
- 5.2 The Condition Field 5-
- 5.3 Branch and Branch with link (B, BL) 5-
- 5.4 Data Processing 5-
- 5.5 PSR Transfer (MRS, MSR) 5-
- 5.6 Multiply and Multiply-Accumulate (MUL, MLA) 5-
- 5.7 Single Data Transfer (LDR, STR) 5-
- 5.8 Block Data Transfer (LDM, STM) 5- Preliminary
- 5.9 Single Data Swap (SWP) 5-
- 5.10 Software Interrupt (SWI) 5-
- 5.11 Coprocessor Instructions 5-
- 5.12 Coprocessor data operations (CDP) 5-
- 5.13 Coprocessor Data Transfers (LDC, STC) 5-
- 5.14 Coprocessor Register Transfers (MRC, MCR) 5-
- 5.15 Undefined Instruction 5-
- 5.16 Instruction Set Examples 5-
- 5.17 Instruction Speed Summary 5-
- 6 Cache, Write Buffer and Coprocessors 6-
- 6.1 Instruction and Data Cache 6-
- 6.2 Read-lock-write 6-
- 6.3 IDC Enable/Disable and Reset 6-
- 6.4 Write Buffer 6-
- 6.5 Coprocessors 6-
- 7 ARM Processor MMU 7-
- 7.1 Introduction 7-
- 7.2 MMU Program Accessible Registers 7-
- 7.3 Address Translation 7-
- 7.4 Translation Process 7-
- 7.5 Translating Section References 7-
- 7.6 Translating Small Page References 7-
- 7.7 Translating Large Page References 7-
- 7.8 MMU Faults and CPU Aborts 7-
- 7.9 Fault Address and Fault Status Registers (FAR and FSR)7-
- 7.10 Domain Access Control 7-
- 7.11 Fault Checking Sequence 7-
- 7.12 Interaction of the MMU, IDC and Write Buffer 7-
- 7.13 Effect of Reset 7-
- 8 ARM7100 Programmer’s Model 8-
- 8.1 Introduction 8-
- 8.2 Summary of Registers 8-
- 8.3 Register Descriptions 8-
- 9 Interrupt Controller 9-
- 9.1 Interrupt Controller 9-
- 10 The Expansion and ROM Interface 10-
- 10.1 The Expansion and ROM Interface 10-
- 11 DRAM controller 11-
- 12 CODEC Interface 12-
- 13 Synchronous Serial Interface 13-
- 13.1 Synchronous Serial Interface 13-
- 14 LCD Controller 14-
- 15 UART and SiR Encoder 15- Preliminary
- 15.1 UART 15-
- 15.2 SiR Encoder 15-
- 16 Timer Counters 16-
- 16.1 Timer Counters 16-
- 16.2 Real Time Clock 16-
- 17 DC to DC Converters 17-
- 17.1 DC to DC Converter Interfaces 17-
- 18 Power Management and Reset 18-
- 18.1 State Control 18-
- 18.2 Reset 18-
- 19 Memory Map 19-
- 20 DC and AC Parameters 20-
- 20.1 Absolute Maximum Ratings 20-
- 20.2 DC Operating Conditions 20-
- 20.3 DC Characteristics 20-
- 20.4 AC Characteristics 20-
- 21 Physical Details 21-
- 21.1 Pin diagrams for the ARM7100 21-
- 22 Pinout 22-
ARM7100 Data Sheet
1
Preliminary
Introduction
This chapter provides an introduction to the ARM7100. 1.1 Introduction 1- 1.2 System Description 1- 1.3 Block Diagram 1- 1.4 CPU Core 1- 1.5 Datasheet Notation 1-
1
Introduction
ARM7100 Data Sheet
Preliminary
1.1 Introduction
The ARM7100 is a highly integrated single chip microcontroller for PDA products, using modular design techniques based on the Advanced Microcontroller Bus Architecture (AMBA) to simplify design and test while optimizing for lowest power (70mW) and low die size. The ARM7100 delivers 18.4 MIPS (peak) at 3.3V and contains an embedded ARM710a core (including 8kByte cache and MMU) with ARM- library peripherals such as an LCD controller, UART and CODEC interface.
1.2 System Description
ARM7100 is based around the ARM710a processor core. The principle functional blocks in ARM7100 are:
- ARM7 CPU core
- memory management unit
- 8Kb of unified instruction and data cache
- interrupt and fast interrupt controller
- expansion and ROM interface giving 8 x 256 Mb expansion segments with independent wait state control
- DRAM controller supporting fast page mode and self refresh in standby
- 36 bits of general purpose peripheral I/O
- telephony CODEC interface with 16-byte FIFOs
- programmable 4-bit per pixel LCD controller
- full duplex UART and two 16-byte FIFOs plus logic to implement the IrDA SIR protocol; capable of speeds up to 115K bits per second
- two 16-bit general purpose counter timers
- A 32-bit real time clock and comparator
- two DC to DC converter interfaces
- system state control and power management
- synchronous serial interface for Microwire or SPI peripherals such as ADCs
- pin test and device isolation logic
- external tracing support for debug
- a main 3.68MHz oscillator with PLL to create system frequency of 18.432MHz
- a low power 32.768 KHz oscillator ò Figure 1-1: ARM7100 block diagram on page 1-3 shows a simplified block diagram of ARM7100.
Introduction
ARM7100 Data Sheet
Preliminary
1.4 CPU Core
The processor macrocell contains the ARM7 processor core with 8Kb of cache, memory management unit and write buffer. See òChapter 3, The ARM Processor Macrocell for a description of the ARM processor macrocell.
1.5 Datasheet Notation
0x marks a Hexadecimal quantity
BOLD external signals are shown in bold capital letters
binary where it is not clear that a quantity is binary, it is followed by the word binary
ARM7100 Data Sheet
1
Preliminary
Signal Description
This chapter gives the name, type and relevant details of each of the ARM7100 signals. 2.1 Signal Descriptions 2-
2
Signal Description
ARM7100 Data Sheet
Preliminary
nEXTPWR I External power sense. Must be driven LOW if the system is powered by external source.
nBATCHG I New battery sense. Should be driven LOW if battery voltage falls below the no-battery threshold.
nPOR IS Power-on reset input. Active LOW input completely resets the system.
RUN O System active output. HIGH when system is active or idle, LOW while in the standby state.
WAKEUP IS Wake up input signal. Rising edge forces system into operating state.
nURESET IS User reset input. Active LOW input.
PCMCK O CODEC clock output.
PCMSYNC O CODEC synchronisation pulse output.
PCMOUT O CODEC serial data output.
PCMIN I CODEC serial data input.
ADCCLK O Synchronous serial interface ADC clock output.
SMPLCK O Synchronous serial interface ADC sample clock, can be disabled.
nADCCS O Synchronous serial interface ADC active LOW chip select and synchronisation output.
ADCOUT O Synchronous serial interface ADC serial data output.
ADCIN I Synchronous serial interface ADC serial data input.
LEDDRV O Infra-red LED drive output.
PHDIN I Infra-red photo diode input.
TXD O RS232 Tx output.
RXD I RS232 Rx input.
DSR I RS232 DSR input.
DCD I RS232 DCD input.
CTS I RS232 CTS input.
DD[0:3] O LCD display data.
CL1 O LCD line clock.
CL2 O LCD pixel clock.
FRM O LCD frame synchronisation pulse output.
M O LCD AC bias drive.
Name Type Description:
Table 2-1: Signal descriptions (Continued)
Signal Description
ARM7100 Data Sheet
Preliminary
Key to signal types and drive capabilities
I Input
IS Schmitt input
IP Input with internal pull-up
O Standard drive output
OM Medium drive output
IOVH Very high drive I/O
IO Standard drive I/O
IOH High drive I/O See ò 20.3 DC Characteristics on page 20-3 for more details.
COL[0:7] O Keyboard column drives.
BUZ O This output is driven by direct software control, or can be driven by a frequency generated by timer counter interrupts. It is designed to drive a buzzer.
PA[0:7] IO Port A I/O.
PB[0:7] IO Port B I/O.
PC[0:7] IO Port C I/O.
PD[0:3] IO Port D I/O.
PD[4:7] IOH Port D high drive I/O
PE[0:3] IO Port E I/O.
DRIVE[0:1] IOVH DC to DC drive outputs.
FB[0:1] I DC to DC feedback inputs.
nTEST[0:1] IP Test mode select inputs (always HIGH for normal operation).
MOSCIN/OUT - Main 3.6864MHz oscillator for 18.432 MHz PLL.
RTCIN/OUT - Real time clock 32.768 KHz oscillator.
Name Type Description:
Table 2-1: Signal descriptions (Continued)
The ARM Processor Macrocell
ARM7100 Data Sheet
Preliminary
3.1 Introduction
ARM7100 contains a 32-bit RISC ARM710a processor macrocell. It has a 8Kb cache, write buffer, and a memory management unit (MMU). The ARM processor macrocell offers high-level RISC performance, yet its fully static design ensures minimal power consumption. This makes it ideal for incorporation into ARM7100. This part of the datasheet describes the features of the ARM processor macrocell which are available to the user in its embedded state within ARM7100. It is not intended that this should be used as a standalone datasheet for a separate ARM processor macrocell.
3.1.1 Architecture
The ARM processor architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are greatly simplified compared with microprogrammed Complex Instruction Set Computers (CISC). The mixed data and instruction cache together with the write buffer substantially raise the average execution speed and reduce the average amount of memory bandwidth required by the processor. The MMU supports a conventional two-level page-table structure and a number of extensions which make it ideal for embedded control, UNIX and Object Oriented systems.
3.2 Instruction set
The instruction set comprises ten basic instruction types:
- two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform high-speed operations on the data in a bank of 31 registers, each 32 bits wide
- three classes of instruction control data transfer between memory and the registers, one optimized for flexibility of addressing, another for rapid context switching and the third for swapping data
- two instructions control the flow and privilege level of execution
- three types are dedicated to the control of external coprocessors which allow the functionality of the instruction set to be extended in an open and uniform way. However, as for the ARM710, the facility to add external coprocessors to the ARM7100 is not available, and software emulation of coprocessor activity will be required if these instructions are to perform a defined function. The ARM instruction set is a good target for compilers of many different high-level languages. Where required for critical code segments, assembly code programming is also straightforward, unlike some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies.
The ARM Processor Macrocell
ARM7100 Data Sheet
Preliminary
3.3 Memory Interface
The memory interface has been designed to allow the performance potential to be realised without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals permit ARM7100 to exploit the page mode access offered by industry-standard DRAMs.
3.4 Clocking
ARM7100 uses the ARM processor macrocell in fastbus mode. This means that the core FCLK frequency is tied to the main processor input clock ( MCLK ). All references to FCLK in this datasheet should be read as MCLK.
3.5 ARM Processor Block Diagram
Figure 3-1: ARM processor block diagram
MMU
8KByte Cache
ARM
CPU
Write Buffer
Address Buffer (^) C o n t r o l
Clock
MCLK SNA FCLK NRESET
NMREQ
NIRQ NFIQ
Internal Data Bus
DBE D[31:0]
Internal Address Bus
C o p r o c
A[31:0] NR/W NB/W
ARM7100 Data Sheet
1
Preliminary
The ARM Processor
Programmer's Model
This chapter describes the programmer’s model. 4.1 Introduction 4- 4.2 Register Configuration 4- 4.3 Operating Mode Selection 4- 4.4 Registers 4- 4.5 Exceptions 4- 4.6 Configuration Control Registers 4- 4.7 Reset 4-
4
The ARM Processor Programmer's Model
ARM7100 Data Sheet
Preliminary
4.1 Introduction
The ARM processor supports a variety of operating configurations. Some are controlled by register bits and are known as theregister configurations. Others may be controlled by software and these are known asoperating modes.
4.2 Register Configuration
The ARM processor provides 3 register configuration settings which may be changed while the processor is running. These are discussed below.
4.2.1 Big and little-endian (the bigend bit)
The bigend bit in the control register sets whether the ARM7100 treats words in memory as being stored in big-endian or little-endian format. See òChapter 6, Cache, Write Buffer and Coprocessors for more information on the Control Register. Memory is viewed as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. In the little-endian scheme the lowest numbered byte in a word is considered to be the least significant byte of the word and the highest numbered byte is the most significant. Byte 0 of the memory system should be connected to data lines 7 through 0 ( D[7:0] ) in this scheme.
Figure 4-1: Little-endian addresses of bytes within word In the big-endian scheme the most significant byte of a word is stored at the lowest numbered byte and the least significant byte is stored at the highest numbered byte. Byte 0 of the memory system should therefore be connected to data lines 31 through 24 ( D[31:24] ). Load and store are the only instructions affected by the endianness: see ò 5.7 Single Data Transfer (LDR, STR) on page 5-21 for more details.
Little-endian
Higher Address 31 24 23 16 15 8 7 0 Word Address
11 10 9 8 8
7 6 5 4 4
3 2 1 0 0
Lower Address
- Least significant byte is at lowest address
- Word is addressed by byte address of least significant byte
