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Question 1. Which organization is primarily responsible for maintaining the RISC-V ISA specifications? A) IEEE B) RISC-V International C) ISO D) The Open Source Initiative Answer: B Explanation: RISC-V International (formerly RISC-V Foundation) governs the ISA, publishes specifications, and coordinates extensions. Question 2. In the RISC-V naming convention, what does the “M” in RV64IM signify? A) Memory-mapped I/O B) Integer Multiplication/Division extension C) Machine-mode only D) Macro-instruction support Answer: B Explanation: “M” denotes the standard integer multiplication and division extension. Question 3. Which register is hard-wired to zero in all RISC-V implementations? A) x B) x C) x D) x Answer: A Explanation: Register x0 always reads as zero and writes to it are ignored. Question 4. Which of the following is a compressed-instruction format in RISC-V? A) R-type 32-bit B) C-type 16-bit
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C) J-type 32-bit D) S-type 32-bit Answer: B Explanation: The C-type format encodes a subset of instructions in 16 bits to reduce code size. Question 5. What privilege level is typically used for an operating system kernel on a general-purpose RISC-V processor? A) User (U) B) Supervisor (S) C) Hypervisor (H) D) Machine (M) Answer: B Explanation: The Supervisor mode provides privileged access for OS kernels while allowing user processes to run in U-mode. Question 6. Which CSR holds the program counter to return to after handling an exception? A) mtvec B) mepc C) mcause D) mip Answer: B Explanation: The mepc CSR stores the address of the instruction that caused the trap. Question 7. In the RV32I base ISA, which instruction format is used for load operations? A) R-type B) I-type C) S-type D) B-type Answer: B
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B) 3
C) 4
D) 5
Answer: B Explanation: Sv39 uses a three-level page-table hierarchy to translate 39-bit virtual addresses. Question 12. Which standard extension provides atomic read-modify-write instructions? A) F B) D C) A D) C Answer: C Explanation: The “A” extension adds atomic instructions such as lr.w, sc.w, amoswap.w, etc. Question 13. Which of the following is a valid RISC-V branch instruction? A) beqz B) beq C) bgt D) bltui Answer: B Explanation: “beq rs1, rs2, offset” is the standard equality branch; other forms are not defined. Question 14. What does the “ecall” instruction trigger? A) A software interrupt for system calls B) A hardware exception for illegal instruction C) A jump to the reset vector D) A cache flush operation Answer: A
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Explanation: “ecall” causes a synchronous trap to the operating system for a system call. Question 15. Which of the following registers is caller-saved according to the RISC-V ABI? A) s0 (fp) B) s C) a D) ra (x1) Answer: C Explanation: Argument registers a0-a7 are caller-saved; the callee must preserve s0-s11 and ra. Question 16. In the RISC-V privileged architecture, which CSR controls the current privilege mode? A) mstatus B) medeleg C) mip D) sie Answer: A Explanation: Bits in mstatus (MPP, MPP, etc.) define the current privilege level and previous mode. Question 17. Which instruction format is used for the “jal” (jump-and-link) instruction? A) R-type B) I-type C) J-type D) U-type Answer: C Explanation: “jal” uses the J-type format, encoding a 20-bit signed immediate for the target address.
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D) No ordering guarantees Answer: A Explanation: Single-core execution follows sequential consistency; ordering only relaxes on multi-core with explicit fences. Question 22. Which pseudo-instruction is equivalent to “addi rd, rd, 0”? A) mv rd, rs B) nop C) li rd, 0 D) ret Answer: A Explanation: “mv rd, rs” copies rs to rd; it expands to “addi rd, rs, 0”. Question 23. Which of the following CSRs holds the cause of the most recent trap? A) mstatus B) mcause C) mtval D) mip Answer: B Explanation: mcause encodes whether the trap was an exception or interrupt and its identifying code. Question 24. What is the default alignment requirement for RISC-V 32-bit instructions in memory? A) 2-byte B) 4-byte C) 8-byte D) No alignment required Answer: B Explanation: All 32-bit instructions must be aligned on a 4-byte boundary.
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Question 25. Which of the following is a valid way to encode a 64-bit immediate value in RV64I? A) A single “lui” instruction B) “addi” with a 12-bit immediate only C) A pair of “lui” and “addi” instructions D) Immediate values cannot exceed 12 bits in RV64I Answer: C Explanation: Large immediates are built by loading the upper 20 bits with “lui” then adding the low 12 bits with “addi”. Question 26. In RISC-V, which instruction is used to read a CSR into a general-purpose register? A) csrrw B) csrrs C) csrrc D) csrrwi Answer: B Explanation: csrrs reads the CSR and optionally sets bits; csrrw also writes, but csrrs alone can be used for a read. Question 27. Which of the following is a correct way to implement a loop that counts from 0 to 9 in RISC-V assembly? A) addi t0, t0, 1; blt t0, ten, loop B) addi t0, t0, -1; bgt t0, zero, loop C) li t0, 10; beq t0, zero, exit D) li t0, 0; bge t0, ten, exit; addi t0, t0, 1; j loop Answer: A Explanation: Increment t0 each iteration and branch if t0 < 10 (label “ten”) back to the loop. Question 28. What does the “.section .bss” directive indicate? A) Read-only data B) Initialized data
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Question 32. What is the effect of the “fence.i” instruction? A) Flushes the instruction cache B) Serializes memory writes C) Clears the floating-point registers D) Triggers a software interrupt Answer: A Explanation: fence.i ensures that any self-modifying code written to memory becomes visible to the instruction fetch unit. Question 33. Which of the following describes the “RV32E” ISA? A) A reduced-register variant with 16 integer registers B) An extension for embedded floating-point C) A version that includes vector instructions D) A privileged-mode only ISA Answer: A Explanation: RV32E eliminates registers x8-x15, leaving only 16 integer registers for very small cores. Question 34. In the context of RISC-V, what does “ratified” mean for a specification? A) It is still under public review B) It has been formally approved and frozen for implementation C) It is deprecated and should not be used D) It is a draft version only for experimental use Answer: B Explanation: A ratified spec has passed the voting process and is considered stable for implementation. Question 35. Which instruction format uses a 7-bit opcode, 5-bit rd, and a 20 - bit immediate? A) U-type B) J-type
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C) I-type D) R-type Answer: A Explanation: U-type encodes upper-immediate instructions like “lui” and “auipc”. Question 36. Which of the following is a correct way to perform a 64-bit multiplication in RV64IM? A) mulw rd, rs1, rs B) mul rd, rs1, rs C) mulh rd, rs1, rs D) mulhu rd, rs1, rs Answer: B Explanation: “mul” computes the full 64-bit product; “mulw” operates on the lower 32 bits. Question 37. What does the “.global main” directive accomplish? A) Declares a global variable named main B) Marks the label “main” as visible to the linker as an entry point C) Allocates memory for the main function D) Sets the program’s execution mode to user Answer: B Explanation: .global (or .globl) makes the symbol visible to other translation units and the linker. Question 38. Which of the following is a valid RISC-V vector extension prefix? A) V B) Z C) X D) Y Answer: B Explanation: Vector extensions are defined under the “Z” namespace, e.g., “Zve64d”.
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B) Supervisor (S) C) Hypervisor (H) D) Machine (M) Answer: D Explanation: Machine mode can access all resources and configure lower privilege modes. Question 43. What does the “csrrwi rd, csr, zimm” instruction do? A) Writes an immediate to a CSR and writes the old CSR value to rd B) Reads a CSR into rd without modification C. Writes rd into the CSR and zero-extends the result D) Clears bits in the CSR specified by zimm Answer: A Explanation: csrrwi writes the zero-extended immediate (zimm) to the CSR and returns the previous CSR value in rd. Question 44. Which of the following statements about the “jalr” instruction is true? A) It always jumps to an absolute address B) It adds an immediate to rs1, masks the LSB, and jumps to the result C) It can only be used in Machine mode D) It does not write a return address to rd Answer: B Explanation: jalr computes target = (rs1 + imm) & ~1, then jumps, storing the next PC in rd. Question 45. Which compiler flag tells GCC to generate code for the RV64GC ISA? A) -march=rv64imafd B) -march=rv64gc C) -march=rv32i D) -march=rv64imc Answer: B
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Explanation: “rv64gc” denotes RV64 with the standard extensions (I, M, A, F, D, C). Question 46. In RISC-V assembly, which directive is used to place data in a read-only section? A) .rodata B) .data C) .bss D) .text Answer: A Explanation: .rodata creates a read-only data section, often placed after .text. Question 47. Which of the following is NOT a standard RISC-V exception type? A) Instruction address misaligned B. Page fault on load C. Illegal instruction D. Cache coherence violation Answer: D Explanation: Cache coherence violations are not defined as architectural exceptions in RISC-V. Question 48. What is the purpose of the “mret” instruction? A) Return from a machine-mode trap to the previous privilege level B) Enter machine mode from any lower mode C) Reset the processor D) Flush the memory hierarchy Answer: A Explanation: mret restores the previous privilege mode and PC from mepc and mstatus. Question 49. In the RISC-V ABI, which registers are considered callee-saved? A) a0-a
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Explanation: “ecall” triggers a system-call trap; the kernel examines a7 to determine the call number. Question 53. Which of the following statements about the “RV32IMAFD” ISA is correct? A. It includes the compressed “C” extension B. It supports double-precision floating-point but not single-precision C. It provides integer multiplication, atomic, single- and double-precision FP D. It is a 64-bit ISA Answer: C Explanation: The suffix “AFD” indicates single- and double-precision FP; “M” and “A” are integer multiply/divide and atomic extensions. Question 54. In the RISC-V privileged spec, which CSR holds the pending interrupt bits? A. mip B. mie C. mstatus D. mtval Answer: A Explanation: mip contains the pending interrupt bits for Machine mode. Question 55. Which of the following is a correct way to define a 32-bit constant in the .data section? A. .word 0x B. .dword 0x C. .byte 0x12,0x34,0x56,0x D. .half 0x Answer: A Explanation: .word defines a 32-bit value; .dword is 64-bit, .half is 16-bit. Question 56. What does the “sret” instruction do? A. Return from a supervisor-mode trap to the previous mode
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B. Switch execution to supervisor mode unconditionally C. Reset the processor’s status registers D. Perform a secure return to machine mode only Answer: A Explanation: sret restores the previous privilege level (usually User) from the supervisor trap. Question 57. Which of the following is a valid reason to use the “.align 3” directive before a function? A. To ensure the function starts at a 2-byte boundary B. To align the function on an 8-byte boundary for performance C. To place the function in a separate memory segment D. To guarantee the function will be placed at address 0x Answer: B Explanation: .align 3 aligns to 2³ = 8 bytes, which can improve instruction fetch efficiency. Question 58. In RISC-V, which instruction can be used to atomically set bits in a memory location? A. amoswap.w B. amoor.w C. amoadd.w D. amoxor.w Answer: B Explanation: amoor.w performs an atomic OR, setting bits specified by the source register. Question 59. Which of the following best describes the role of “OpenOCD” in RISC-V development? A. A compiler that generates RISC-V binaries B. A simulator for running RISC-V code on a PC C. A debugging server that interfaces with JTAG probes D. An operating system for embedded RISC-V devices
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Question 63. Which of the following is true about the “RV32IMC” ISA? A. It includes double-precision floating-point. B. It provides compressed 16-bit instructions. C. It is a 64-bit ISA. D. It lacks the integer multiplication extension. Answer: B Explanation: The “C” suffix indicates the presence of the compressed instruction set. Question 64. Which of the following registers is used to hold the value of the most recent exception program counter in Supervisor mode? A. sepc B. stvec C. scause D. sip Answer: A Explanation: sepc stores the PC of the instruction that caused a trap while in Supervisor mode. Question 65. In RISC-V assembly, which pseudo-instruction expands to “addi rd, x0, 0”? A. nop B. li rd, 0 C. mv rd, x D. ret Answer: A Explanation: “nop” is defined as “addi x0, x0, 0”, which does nothing but occupies an instruction slot. Question 66. Which of the following is a characteristic of the “Sv39” page-table entry format? A. Each entry is 128 bits long. B. The PPN field is split into three parts: PPN[2], PPN[1], PPN[0].
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C. It supports 1 GB superpages only. D. It is used exclusively on 32-bit cores. Answer: B Explanation: Sv39 entries contain a three-part physical page number (PPN) to address 39-bit physical memory. Question 67. Which instruction is used to synchronize memory accesses on RISC-V? A. fence B. sync C. mfence D. barrier Answer: A Explanation: The “fence” instruction orders memory and I/O operations according to its predecessor/successor masks. Question 68. Which of the following statements about the “RV64GC” ISA is correct? A. It includes the “C” compressed extension but not the “M” extension. B. It is a 64-bit ISA with integer, multiplication, atomic, single- and double-precision FP, and compressed extensions. C. It only supports single-precision floating-point. D. It is a proprietary extension not part of the official spec. Answer: B Explanation: RV64GC combines the base integer ISA with extensions M, A, F, D, and C. Question 69. Which of the following is the correct syntax for an inline assembly block in GCC for RISC-V that reads the “mcycle” CSR? A. asm volatile ("csrr %0, mcycle" : "=r"(cycles)); B. asm ("mcycle %0" : "=r"(cycles)); C. asm("rdcycle %0" : "=r"(cycles)); D. asm ("read mcycle into %0" : "=r"(cycles)); Answer: A
