Download RISC-V Foundational Associate Beta Exam Questions and Answers and more Exams Technology in PDF only on Docsity!
Question 1. What is RISC-V primarily known as in the computer architecture world? A) A commercial microprocessor B) An open-source instruction set architecture C) A proprietary hardware platform D) A software development tool Answer: B Explanation: RISC-V is an open-source instruction set architecture (ISA), allowing anyone to implement and use it without licensing fees. Question 2. Who manages the ongoing development and ratification of RISC-V specifications? A) Intel Corporation B) RISC-V International C) Apple Inc. D) ARM Holdings Answer: B Explanation: RISC-V International is the non-profit organization responsible for the development and maintenance of RISC-V standards. Question 3. In which academic institution was RISC-V originally developed? A) Massachusetts Institute of Technology B) University of California, Berkeley C) Stanford University D) Carnegie Mellon University Answer: B Explanation: RISC-V was started at UC Berkeley as a research project to design a simple and open ISA. Question 4. Which document should you consult for the official and most current RISC-V ISA specifications? A) RISC-V Wikipedia page B) RISC-V International website documentation
C) Any open-source forum D) Vendor-specific datasheets Answer: B Explanation: The official RISC-V International website provides up-to-date documentation for all ratified standards. Question 5. Which of the following is a fundamental design principle of RISC-V? A) Complex instruction set B) Modularity and extensibility C) Proprietary licensing D) Fixed microarchitecture Answer: B Explanation: RISC-V is designed to be modular and extensible, allowing for optional extensions. Question 6. The RISC-V community encourages contributions to the ISA through which of the following? A) Paid licensing agreements B) Open-source contributions and discussion forums C) Secret mailing lists D) No contributions are allowed Answer: B Explanation: RISC-V encourages open contributions via mailing lists, forums, and GitHub repositories. Question 7. Which is the base integer instruction set for RISC-V? A) M B) I C) F D) A Answer: B
A) B
B) D
C) Q
D) F
Answer: B Explanation: The “D” extension adds double-precision (64-bit) floating-point capabilities. Question 12. What does the “A” extension enable in RISC-V? A) Advanced arithmetic B) Atomic instructions C) Application mode D) Address translation Answer: B Explanation: The “A” extension introduces atomic instructions for safe multi-threaded operations. Question 13. Which privilege mode in RISC-V has the highest level of authority? A) User mode B) Supervisor mode C) Machine mode D) Hypervisor mode Answer: C Explanation: Machine mode is the highest privilege level, used for low-level hardware control. Question 14. What is the primary use of Supervisor mode in RISC-V? A) Running application code B) Kernel or operating system tasks C) Hardware debugging D) Bootloader initialization Answer: B
Explanation: Supervisor mode is typically used by the OS kernel for system-level tasks. Question 15. Which privilege mode is intended for running ordinary application code? A) User mode B) Machine mode C) Supervisor mode D) Debug mode Answer: A Explanation: User mode isolates applications from direct hardware access and system-level instructions. Question 16. How are Control and Status Registers (CSRs) accessed in RISC-V assembly? A) Using ADD and SUB instructions B) With dedicated CSR instructions such as CSRRW C) By direct memory access D) Through system calls only Answer: B Explanation: CSRs are accessed using specific instructions like CSRRW, CSRRS, and CSRRC. Question 17. Which instruction is used to transfer control to a specific address in RISC-V? A) JAL B) ADDI C) LW D) SW Answer: A Explanation: The JAL (Jump And Link) instruction jumps to a target address and saves the return address. Question 18. What is the primary purpose of the “ecall” instruction in RISC-V? A) Enable cache B) Enter exception handling
Question 22. How many bits wide is a standard RISC-V register in RV32I? A) 8 B) 16 C) 32 D) 64 Answer: C Explanation: In RV32I, registers are 32 bits wide. Question 23. What is the primary purpose of the “jalr” instruction in RISC-V? A) Absolute jump B) Register-indirect jump C) Store a value in memory D) Load a value from memory Answer: B Explanation: “jalr” performs a jump to an address computed from a register and an immediate. Question 24. Which RISC-V instruction is used to load a word from memory into a register? A) SW B) LW C) LUI D) SLL Answer: B Explanation: LW loads a 32-bit word from memory into a register. Question 25. What is the function of the “sw” instruction in RISC-V? A) Store a word from a register to memory B) Switch privilege mode C) Subtract word
D) Start writeback Answer: A Explanation: SW stores a 32-bit word from a register into memory. Question 26. Which instruction type is used to store data from a register to memory? A) I-type B) S-type C) B-type D) R-type Answer: B Explanation: S-type instructions handle memory store operations. Question 27. Which RISC-V instruction is used to create a 32-bit immediate value in a register’s upper bits? A) LUI B) AUIPC C) ADDI D) SLLI Answer: A Explanation: LUI (Load Upper Immediate) loads a 20-bit immediate value into the upper 20 bits of a register. Question 28. What does the AUIPC instruction do in RISC-V? A) Adds upper immediate to PC B) Adds user privilege C) Allocates user instruction pointer cache D) Adjusts user interrupt priority count Answer: A Explanation: AUIPC adds a 20-bit upper immediate value to the program counter and writes the result to a register.
D) Debug mode Answer: C Explanation: Machine mode has unrestricted access to all hardware. Question 33. How many general-purpose integer registers does a standard RISC-V implementation provide? A) 8 B) 16 C) 32 D) 64 Answer: C Explanation: RISC-V defines 32 general-purpose integer registers. Question 34. What is the purpose of the x0 register in RISC-V? A) Temporary storage B) Stack pointer C) Hardwired zero D) Return address Answer: C Explanation: x0 is always zero, regardless of any writes. Question 35. Which register is typically used as the stack pointer in RISC-V? A) x B) x C) x D) x Answer: B Explanation: x2 (sp) is conventionally used as the stack pointer.
Question 36. What happens if you try to write a non-zero value to the x0 register? A) x0 retains the new value B) Causes an exception C) No operation; x0 remains zero D) Resets the processor Answer: C Explanation: Writes to x0 are ignored; it always reads as zero. Question 37. Which RISC-V instruction is used to return from an exception or interrupt? A) RET B) MRET C) JALR D) ECALL Answer: B Explanation: MRET returns from machine-mode exceptions or interrupts. Question 38. Which RISC-V register conventionally holds the return address? A) x B) x C) x D) x Answer: B Explanation: x1 (ra) is used for storing the return address. Question 39. What is the main purpose of CSRs in RISC-V? A) General computation B) Control and status management C) Floating-point operations D) Cache management
B) Little-endian C) Bi-endian D) Endian-agnostic Answer: B Explanation: RISC-V is little-endian by default. Question 44. Which instruction can cause a change in privilege mode in RISC-V? A) JAL B) ECALL C) ADDI D) LW Answer: B Explanation: ECALL can trigger a change to a higher privilege mode for system service handling. Question 45. What is the purpose of the “csrci” instruction family in RISC-V? A) Clear bits in a CSR using an immediate B) Copy a CSR C) Compare and swap D) Cache control Answer: A Explanation: CSRRCI, for example, clears specific bits in a CSR using an immediate value. Question 46. Which instruction format is used for unconditional jumps in RISC-V? A) B-type B) J-type C) S-type D) R-type Answer: B Explanation: J-type format is used for instructions like JAL, which perform unconditional jumps.
Question 47. What is the effect of the “slli” instruction? A) Logical shift left immediate B) Store lower immediate C) Set lower instruction D) Subtract lower immediate Answer: A Explanation: SLLI shifts the bits in a register left by a specified immediate value. Question 48. Which of the following is a valid RISC-V assembly comment? A) // comment B) /* comment */ C) ; comment D) # comment Answer: D Explanation: RISC-V assembly uses “#” for single-line comments. Question 49. What is the default calling convention for passing arguments in RISC-V? A) Stack-based B) Register-based C) Heap-based D) File-based Answer: B Explanation: The default calling convention passes arguments via registers (a0-a7). Question 50. Which registers are used for function arguments and return values? A) t0-t B) s0-s C) a0-a
A) Load byte unsigned B) Load buffer unit C) Logical bit update D) Left byte utilization Answer: A Explanation: “lbu” loads a byte from memory and zero-extends it. Question 55. Which instruction is used to store a halfword to memory? A) SH B) SW C) SB D) SLL Answer: A Explanation: SH stores a 16-bit halfword from a register into memory. Question 56. What is the mnemonic for the unconditional jump-and-link instruction? A) JAL B) JMP C) JUMP D) JLR Answer: A Explanation: JAL jumps to an address and links (stores) the return address. Question 57. Which RISC-V instruction would branch if two registers are not equal? A) BEQ B) BLT C) BNE D) BGE Answer: C
Explanation: BNE (branch if not equal) checks if two registers differ. Question 58. Which CSR holds the current privilege mode and interrupt enable bits in RISC-V? A) mstatus B) mepc C) mtvec D) misa Answer: A Explanation: mstatus stores current processor state, including privilege mode and interrupt status. Question 59. What is the primary function of the “mtvec” CSR? A) Machine trap vector base address B) Machine timer value C) Memory trap verification D) Machine time vector Answer: A Explanation: mtvec holds the base address for machine-mode traps (exceptions or interrupts). Question 60. What does the “mepc” CSR store? A) Machine exception privilege code B) Machine exception program counter C) Memory error protection code D) Machine external privilege control Answer: B Explanation: mepc stores the program counter at the time of an exception. Question 61. Which instruction would you use to write an immediate value into a register? A) ADDI B) LW
Question 65. If you want to perform a logical AND between two registers, which instruction do you use? A) OR B) XOR C) AND D) NAND Answer: C Explanation: “AND” performs a logical AND between two registers. Question 66. What does the “slt” instruction do? A) Sets register to 1 if less than, else 0 (signed comparison) B) Shifts left two C) Sets less than unsigned D) Stores long type Answer: A Explanation: “slt” sets the result register to 1 if the first operand is less than the second (signed). Question 67. In RISC-V, which register is used as the global pointer? A) x B) x C) x D) x Answer: D Explanation: x3 (gp) is the global pointer register. Question 68. Which register is typically used as the frame pointer in a function? A) x B) x C) x D) x
Answer: C Explanation: x8 (s0/fp) is used as the frame pointer. Question 69. What would the instruction “ori x5, x0, 0xFF” do? A) Set x5 to 0xFF B) Set x5 to 0x C) OR x5 with 0xFF D) Output to register 5 Answer: A Explanation: ORI with x0 (zero) and 0xFF sets x5 to 0xFF. Question 70. How is sign extension handled in the “lh” instruction? A) Zero-extends the loaded halfword B) Sign-extends the loaded halfword C) Ignores sign D) Reverses bits Answer: B Explanation: LH loads a 16-bit value and sign-extends it to the register width. Question 71. Which instruction is used to load the address of a label into a register? A) LA (pseudoinstruction) B) LI C) ADDI D) SLLI Answer: A Explanation: LA is a pseudoinstruction for loading addresses. Question 72. What is the purpose of “nop” in RISC-V? A) No operation
