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Question 1. Which university originated the RISC-V project? A) MIT B) Stanford C) UC Berkeley D) Harvard Answer: C Explanation: RISC-V was developed at the University of California, Berkeley, as an open-source instruction set architecture. Question 2. What is the main philosophy behind RISC-V’s design? A) Complex instruction set and high cost B) Modularity, extensibility, and simplicity C) Proprietary and closed-source D) High power consumption Answer: B Explanation: RISC-V emphasizes modularity, extensibility, and simplicity, which differentiates it from many other ISAs. Question 3. Which organization is responsible for maintaining the RISC-V ISA standards? A) OpenISA Foundation B) RISC-V International C) ARM Holdings D) IEEE Answer: B Explanation: RISC-V International is the non-profit organization that oversees and standardizes the RISC- V ISA. Question 4. What is a key difference between RISC-V and ARM ISAs? A) RISC-V is proprietary, ARM is open-source B) RISC-V is open-source, ARM is proprietary
C) Both are open-source D) Both are proprietary Answer: B Explanation: RISC-V is open-source, while ARM is a proprietary instruction set. Question 5. Which of the following is NOT a standard RISC-V extension? A) M (Integer Multiplication/Division) B) A (Atomic Operations) C) Z (Zero Register) D) F (Single-Precision Floating-Point) Answer: C Explanation: Z is not a standard extension; M, A, and F are. Question 6. What does the “RV32I” designation indicate in RISC-V? A) 32-bit floating-point instructions B) 32-bit integer base instruction set C) 64-bit integer base instruction set D) 32-bit compressed instruction set Answer: B Explanation: RV32I stands for the 32-bit Integer base instruction set. Question 7. What is the primary governance structure of RISC-V International? A) For-profit company B) Non-profit organization with working groups C) University-run committee D) Single corporate owner Answer: B Explanation: RISC-V International is a non-profit with various technical working groups guiding development.
C) A
D) C
Answer: B Explanation: The 'D' extension adds double-precision floating-point instructions to the base set. Question 12. In RISC-V, what does the 'C' extension provide? A) Compressed instructions for reduced code size B) Cache management C) Cryptographic operations D) Control and status registers Answer: A Explanation: The 'C' extension introduces compressed instructions, reducing code size and improving efficiency. Question 13. What is the primary focus of the RISC-V base integer instruction set? A) Floating-point arithmetic B) Integer arithmetic and basic operations C) Graphical processing D) Network management Answer: B Explanation: The base integer instruction set (I) provides core integer arithmetic, logical, and control instructions. Question 14. Which company is NOT a member of RISC-V International? A) Google B) Intel C) ARM Holdings D) Western Digital Answer: C
Explanation: ARM Holdings is not a member; it is a competing ISA provider. Question 15. How does RISC-V handle optional extensions? A) All extensions are mandatory B) Extensions are modular and optional C) Only floating-point extensions are optional D) Extensions are proprietary Answer: B Explanation: RISC-V is modular, allowing users to select which extensions to implement. Question 16. What does the “A” extension in RISC-V add? A) Advanced arithmetic B) Atomic instructions C) Address translation D) Asynchronous interrupts Answer: B Explanation: The 'A' extension adds atomic instructions for synchronization in multiprocessor systems. Question 17. Which RISC-V privilege level is typically used for application code? A) Machine B) Supervisor C) User D) Hypervisor Answer: C Explanation: User mode is designed for running unprivileged application code. Question 18. What is the significance of RISC-V’s modularity? A) Forces all vendors to use the same features B) Allows customization for specific use cases
Question 22. What is the primary function of Control and Status Registers (CSRs) in RISC-V? A) Data storage B) Program flow control C) System-level configuration and control D) Interrupt generation Answer: C Explanation: CSRs manage system configuration, status, and control operations. Question 23. What type of memory addressing is used in RISC-V? A) Only absolute addressing B) Register-indirect and immediate addressing C) Virtual and physical addressing D) Only direct addressing Answer: C Explanation: RISC-V supports both virtual and physical addressing schemes. Question 24. What is the role of the “Supervisor” privilege level in RISC-V? A) Direct hardware access B) Operating system services and kernel C) User application execution D) Peripheral management only Answer: B Explanation: Supervisor mode is designed for OS and kernel-level code. Question 25. Which instruction format is used by RISC-V for immediate arithmetic operations? A) R-type B) I-type C) S-type D) J-type
Answer: B Explanation: I-type format is used for instructions with immediate values, such as addi. Question 26. What is the typical use of the RISC-V compressed (C) extension? A) Increase instruction width B) Reduce code size and memory bandwidth C) Increase floating-point performance D) Add new privilege levels Answer: B Explanation: The C extension reduces instruction size, saving memory and improving efficiency. Question 27. How does RISC-V manage exceptions and interrupts? A) Through vector tables and CSRs B) With only hardware flags C) Using software polling D) By ignoring them Answer: A Explanation: RISC-V uses CSRs and vector tables to handle exceptions and interrupts. Question 28. What is a key difference between the RISC and CISC philosophies? A) RISC emphasizes many addressing modes B) CISC uses fewer instructions C) RISC uses simpler, fixed-length instructions D) CISC is always open-source Answer: C Explanation: RISC architectures like RISC-V use simple, fixed-length instructions for efficiency. Question 29. What is the typical register width in RV64I? A) 8 bits
Question 33. Which RISC-V instruction format is used for jump instructions? A) R-type B) I-type C) S-type D) J-type Answer: D Explanation: J-type format is used for jump instructions like jal. Question 34. What is the purpose of the RISC-V “M” extension? A) Matrix math B) Integer multiplication and division C) Memory management D) Machine privilege mode Answer: B Explanation: The M extension adds integer multiplication and division instructions. Question 35. What does “RV” stand for in RISC-V naming? A) Register Vector B) Reduced Vector C) RISC-V D) Register Variable Answer: C Explanation: “RV” is shorthand for RISC-V. Question 36. Which RISC-V instruction is used to load a word from memory to a register? A) sw B) lw C) addi
D) beq Answer: B Explanation: lw (load word) loads a 32-bit word from memory to a register. Question 37. Which RISC-V instruction is used to store a word from a register to memory? A) lw B) sw C) add D) sub Answer: B Explanation: sw (store word) stores a 32-bit word from a register to memory. Question 38. Which RISC-V privilege mode is designed for hypervisors and virtualization? A) Machine B) Supervisor C) User D) Hypervisor Answer: D Explanation: Hypervisor mode (if implemented) is for virtualization; not all RISC-V implementations include it. Question 39. What is the reset address for RISC-V processors typically set to? A) 0x B) 0x C) 0xFFFFFFFF D) 0x Answer: B Explanation: In many RISC-V implementations, the reset address is 0x80000000.
Answer: C Explanation: x2 is conventionally used as the stack pointer (sp). Question 44. What is the instruction format for R-type instructions in RISC-V? A) opcode, rs1, rs2, rd, funct3, funct B) opcode, rd, imm C) opcode, rs1, imm, rd D) opcode, rs2, rd Answer: A Explanation: R-type instructions use opcode, rs1, rs2, rd, funct3, and funct7 fields. Question 45. Which instruction is used for a conditional branch if two registers are equal in RISC-V? A) bne B) beq C) blt D) jal Answer: B Explanation: beq (branch if equal) branches if the values of two registers are equal. Question 46. What is a Control and Status Register (CSR)? A) General-purpose register B) Register for program data C) Special register for system configuration D) Floating-point register Answer: C Explanation: CSRs are special registers used for system configuration and status. Question 47. Which RISC-V register is used as the return address register? A) x
B) x C) x D) x Answer: A Explanation: x1 (ra) holds the return address for function calls. Question 48. How are immediate values encoded in RISC-V instructions? A) Using only register values B) Directly in the instruction fields C) Always stored in memory D) Using a separate instruction Answer: B Explanation: Immediate values are encoded directly within the instruction format. Question 49. In RISC-V assembly, what does the instruction 'addi x5, x0, 10' do? A) Adds 10 to x0 and stores in x B) Adds x5 to x0 and stores in x C) Adds x0 and x10, stores in x D) Adds 10 to x5 and stores in x Answer: A Explanation: 'addi x5, x0, 10' sets x5 to 10 since x0 is always zero. Question 50. What type of instruction is 'jalr' in RISC-V? A) Load B) Store C) Register-indirect jump D) Arithmetic Answer: C Explanation: jalr (jump and link register) performs a register-indirect jump.
D) Compare two registers Answer: C Explanation: csrrw atomically reads and writes a Control and Status Register. Question 55. Which RISC-V instruction is used to return from exceptions? A) ecall B) mret C) fence D) jal Answer: B Explanation: mret (machine return) returns from an exception in machine mode. Question 56. Which RISC-V privilege level is required to access all CSRs? A) User B) Supervisor C) Machine D) Hypervisor Answer: C Explanation: Only machine mode has access to all CSRs. Question 57. What does the 'auipc' instruction do? A) Adds upper immediate to PC B) Arithmetic addition C) Multiplies two registers D) Loads a word from memory Answer: A Explanation: auipc adds a 20-bit immediate to the upper bits of the PC and is used for position- independent code.
Question 58. What does the 'lui' instruction do in RISC-V? A) Loads an upper immediate into a register B) Loads a word from memory C) Links two functions D) Loads from the stack Answer: A Explanation: lui (load upper immediate) loads a 20-bit immediate into the upper bits of a register. Question 59. What is the default base for hexadecimal numbers in RISC-V assembly? A) 2 B) 8 C) 10 D) 16 Answer: D Explanation: Hexadecimal numbers are base 16. Question 60. What is the purpose of the 'nop' instruction in RISC-V? A) Performs a binary operation B) No operation C) Nullify a register D) Not allowed Answer: B Explanation: nop does nothing and is often used for timing or alignment. Question 61. What does the 'jal' instruction store in the return address register? A) 0 B) The jump target address C) The address of the next instruction D) The address after the jump
A) Move memory B) Move data between registers C) Move instruction pointer D) Move to memory Answer: B Explanation: mv is a pseudo-instruction for moving data between registers. Question 66. What does the 'li' pseudo-instruction do in RISC-V assembly? A) Load immediate value into register B) Link instruction C) Load instruction D) Logical increment Answer: A Explanation: li loads an immediate value into a register. Question 67. What is the purpose of the 'ret' pseudo-instruction? A) Return from interrupt B) Return from a function C) Reload register D) Restore exception Answer: B Explanation: ret is a pseudo-instruction for returning from a function, translating to 'jalr x0, x1, 0'. Question 68. What is the maximum immediate value that can be encoded in a 12-bit signed field? A) 255 B) 1023 C) 2047 D) 4095 Answer: C
Explanation: 12-bit signed immediate can represent values from - 2048 to 2047. Question 69. In RISC-V assembly, how are comments denoted? A) // B) # C) ; D) -- Answer: B Explanation: Comments in RISC-V assembly start with the '#' character. Question 70. Which RISC-V instruction performs a logical AND between two registers? A) or B) xor C) and D) add Answer: C Explanation: and performs a bitwise logical AND. Question 71. Which instruction is used to branch if a register is less than another (signed comparison)? A) blt B) bgeu C) bgt D) beq Answer: A Explanation: blt branches if one register is less than another (signed). Question 72. What is the main role of the assembler directive '.text'? A) Start data section B) Start code (text) section
