Replacement Algorithms-Assembly Language, Microprocessors and Computer Architecture-Lecture Slides, Slides of Computer Architecture and Organization

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Replacement Algorithms Direct mapping z No choice z Each block only maps to one line z Replace that line

Replacement Algorithms (Cont) Associative & Set Associative z Hardware implemented algorithm (speed) z Least Recently used (LRU) z e.g. in 2 way set associative z Which of the 2 block is lru? z First in first out (FIFO) z replace block that has been in cache longest z Least frequently used z replace block which has had fewest hits z Random

Write through z

All writes go to main memory as wellas cache z Multiple CPUs can monitor mainmemory traffic to keep local (to CPU)cache up to date z Lots of traffic z Slows down writes

Write back z

Updates initially made in cache only z Update bit for cache slot is set whenupdate occurs z If block is to be replaced, write to mainmemory only if update bit is set z Other caches get out of sync z I/O must access main memory throughcache z 15% of memory references are writes

Cache Coherency (Cont) z

Block Size z Larger blocks reduce # of blocks fit into cache z As block becomes larger, additional word isfarther from requested word z No of caches z Single Versus Two-Level Cache z Use of Second Level cache improves performance z Unified versus split Cache z One for Data other for instructions

Pentium 4 Cache z

80386 – no on chip cache z 80486 – 8k using 16 byte lines and four way set associativeorganization z Pentium (all versions) – two on chip L1 caches z Data & instructions z Pentium III –L3 cache added off chip z Pentium 4 z L1 caches z 8k bytes z 64 byte lines z four way set associative z L2 cache z Feeding both L1 caches z 256k z 128 byte lines z 8 way set associative z L3 cache

Pentium 4 Diagram (Simplified)

Pentium 4 Core Processor z

Fetch/Decode Unit z Fetches instructions from L2 cache z Decode into micro-ops z Store micro-ops in L1 cache z Out of order execution logic z Schedules micro-ops z Based on data dependence and resources z May speculatively execute z Execution units z Execute micro-ops z Data from L1 cache z Results in registers z Memory subsystem z L2 cache and systems bus

Power PC Cache Organization z

601 – single 32kb 8 way set associative z 603 – 16kb (2 x 8kb) two way set associative z 604 – 32kb z 610 – 64kb z G3 & G4 z 64kb L1 cache z 8 way set associative z 256k, 512k or 1M L2 cache z two way set associative

• PowerPC G