VHDL Sequential Statements: if, case, loops, and assertions, Slides of Computer Science

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Sequential Statements

Sequential Statement

• These statements can appear inside a process description : - variable assignments - if-then-else - Case - Loop - infinite loop - while loop - for loop - assertion and report - signal assignments - function and procedure calls

Sequential Statement-if

• examples

if sel = 0 then

result <= input_0; -- executed if sel = 0

else

result <= input_1; -- executed if sel /= 0

end i f;

• more examples see sources

entity thermostat is port ( desired_temp, actual_temp : in integer; heater_on : out boolean ); end entity thermostat;

---

architecture example of thermostat is begin

controller : process (desired_temp, actual_temp) is begin if actual_temp < desired_temp - 2 then heater_on <= true; elsif actual_temp > desired_temp + 2 then heater_on <= false; end if; end process controller;

end architecture example; Docsity.com

Sequential Statement-case

type alu_func is (pass1, pass2, add, sub);

case func is

when pass1 => res := op1;

when pass2 => res := op2;

when add => res := op1 + op2;

when sub => res = op1 – op2;

end case;

Sequential Statement-case

type opcodes is (nop, add, sub, ld, st, jmp, br, halt);

case opcode is

when ld | add | sub => op := mem_op;

when st | jmp => op := add_op;

when others => op := 0;

end case;

Sequential Statement-case

• All possible values of the selector

expression must be covered by one and

only one choice

• The values in the choices must be locally

static, (known at analysis stage)

• If the others choice is used, it must be the

last alternative and the only choice in the

alternative.

library ieee; use ieee.std_logic_1164.all;

entity mux4 is

port ( sel : in sel_range; d0, d1, d2, d3 : in std_ulogic; z : out std_ulogic );

end entity mux4;

architecture demo of mux4 is

begin

out_select : process (sel, d0, d1, d2, d3) is begin case sel is when 0 => z <= d0; when 1 => z <= d1; when 2 => z <= d2; when 3 => z <= d3; end case; end process out_select;

end architecture demo; Docsity.com

Sequential Statement-null

• Define a process to be implemented later

control_section : process ( sensitivity_list )

is

begin

null;

end process control_section;

Sequential Statement-loop

• VHDL provides three types of loop or

iterative constructs:

• infinite loop
• while loop
• for loop

entity counter is

port ( clk : in bit; count : out natural );

end entity counter;

architecture behavior of counter is

begin

incrementer : process is variable count_value : natural := 0; begin count <= count_value; loop wait until clk = '1'; count_value := (count_value + 1) mod 16; count <= count_value; end loop; end process incrementer;

end architecture behavior; Docsity.com

Sequential Statement-exit

• Exit statement can be used to “exit” or “jump out” of any loop.
• EBNF: exit_stmt <= [label : ] exit [ loop_label : ] [ when boolean_expr ] ;
• Example:

LoopName: loop … exit LoopName; … end loop;

Sequential Statement-exit

• Example:

loop

… exit ; -- jumps out of the inner most loop …

end loop;

…… -- exit causes the execution to start from this statement onwards

Sequential Statement-exit

• More examples:

exit loop1; -- jumps out of loop

-- with label loop

exit when x = 1; -- jumps out of inner

-- most loop when -- condition is true