University of California, Santa Barbara
Dept. of Electrical and Computer Engineering
ECE154 – Computer Architecture
Homework #4 – due Friday, November 9, 2007
Single Cycle Processor
1. (35 points) We want to add the following instructions to the single cycle datapath described
in class and Chapter 5 of the book. Add any necessary datapath components and control
signals to the single cycle datapath on the next page (same as Figure 5.17, page 307).
Describe the settings of all the control signals.
a. (15 points) "Split Register": This instruction would read an operand from $rs and move
its lower half to $rd with the upper half set to zero. It would also take the upper half of
$rs, shift it right 16 bits (with zero fill), and write it to $rt.
b. (20 points) “Load Word, Variable Offset” lwvo $rd, $rs($rt) would form an address by
adding $t1 and $t2, then use that address to read a word from data memory into $t0.
Registers $t0, $t1, and $t2 are just examples; the instruction should work with any
combination of three GPR's. Briefly explain the changes required to support swvo (store
word, variable offset") instruction that added two GPR's to form an address and used a
third GPR as a data source.
2. (15 points) Patterson and Hennessy 5.2, 5.3
3. (10 points) Patterson and Hennessy 5.14
Multiple Cycle Processor
4. (30 points) Patterson and Hennessy 5.32, 5.33 (Figures 5.28 and 5.38 reproduced on
following pages for your convenience)
5. (15 points) Patterson and Hennessy 5.31
6. (15 points) Patterson and Hennessy 5.36
