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CPSC 2105 Introduction to Computer Organization
Homework Set 9 Due Monday, April 10, 2006
HOMEWORK KEY WITH ANSWERS AND COMMENTS.
The following problems were assigned from Chapter 6 of the textbook Problems 6, 8, 9, 11, and 12. These are found on pages 268 – 270 of the textbook.
- A 2–way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b) Compute the hit ratio for a program that loops 3 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. ANSWER: First note that the memory contains 16 K words, or 2^14 words. As each word is assumed to be addressable, we need a 14–bit address. a) This is a variant of Direct Mapping, so we use the same address format. The only difference is that what is called “Block Number” in Direct Mapping caches is called “Set Number” in Set Associative caches. Each memory block, hence every cache block, holds eight words. But 8 = 2^3. For this reason, the word address part has 3 bits. There are four sets in the cache. Since 4 = 2^2 , we need 2 bits for the set address. There are 14 – (2 + 3) = 14 – 5 = 9 bits in the tag field. Bit Number 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Tag Set Word Our work will be simplified if we allocate word addresses to the four sets. Set 0: 0 – 7, 32 – 39 Set 1: 8 – 15, 40 – 47 This covers the range 8 to 51. Set 2: 16 – 23 48 – 55 Set 3: 24 – 31, 56 – 63 The next table shows the detailed address break–out for word addresses 8 through 51.
In order to maintain some clarity in the tables, we first show the address fields. Address Tag Set Word Offset 8 0000 00000 01 000 0 1 0 9 0000 00000 01 001 0 1 1 10 0000 00000 01 010 0 1 2 11 0000 00000 01 011 0 1 3 12 0000 00000 01 100 0 1 4 13 0000 00000 01 101 0 1 5 14 0000 00000 01 110 0 1 6 15 0000 00000 01 111 0 1 7 16 0000 00000 10 000 0 2 0 17 0000 00000 10 001 0 2 1 18 0000 00000 10 010 0 2 2 19 0000 00000 10 011 0 2 3 20 0000 00000 10 100 0 2 4 21 0000 00000 10 101 0 2 5 22 0000 00000 10 110 0 2 6 23 0000 00000 10 111 0 2 7 24 0000 00000 11 000 0 3 0 25 0000 00000 11 001 0 3 1 26 0000 00000 11 010 0 3 2 27 0000 00000 11 011 0 3 3 28 0000 00000 11 100 0 3 4 29 0000 00000 11 101 0 3 5 30 0000 00000 11 110 0 3 6 31 0000 00000 11 111 0 3 7 32 0000 00001 00 000 1 0 0 33 0000 00001 00 001 1 0 1 34 0000 00001 00 010 1 0 2 35 0000 00001 00 011 1 0 3 36 0000 00001 00 100 1 0 4 37 0000 00001 00 101 1 0 5 38 0000 00001 00 110 1 0 6 39 0000 00001 00 111 1 0 7 40 0000 00001 01 000 1 1 0 41 0000 00001 01 001 1 1 1 42 0000 00001 01 010 1 1 2 43 0000 00001 01 011 1 1 3 44 0000 00001 01 100 1 1 4 45 0000 00001 01 101 1 1 5 46 0000 00001 01 110 1 1 6 47 0000 00001 01 111 1 1 7 48 0000 00001 10 000 1 2 0 49 0000 00001 10 001 1 2 1 50 0000 00001 10 010 1 2 2 51 0000 00001 10 011 1 2 3
Access word at address 32 Cache Miss Tag = 0, Set = 0, Offset = 0 Block 0 of Set Block 1 of Set Set Tag Contents Tag Contents 0 32, 33, 34, 35, 36, 37, 38, 39 1 0 8, 9, 10, 11, 12, 13, 14, 15 2 16, 17, 18, 19, 20, 21, 22, 23 3 24, 25, 26, 27, 28, 29, 30, 31 Seven accesses: words at addresses 33 through 39: Seven cache hits. Total cache misses = 4. Total cache hits = 28. Hit Ratio = 7 / 8. Access word at address 40 Cache Miss Tag = 0, Set = 1, Offset = 0 Block 0 of Set Block 1 of Set Set Tag Contents Tag Contents 0 32, 33, 34, 35, 36, 37, 38, 39 1 0 8, 9, 10, 11, 12, 13, 14, 15 40, 41, 42, 43, 44, 45, 46, 47 2 16, 17, 18, 19, 20, 21, 22, 23 3 24, 25, 26, 27, 28, 29, 30, 31 Seven accesses: words at addresses 41 through 47: Seven cache hits. Total cache misses = 5. Total cache hits = 35. Hit Ratio = 7 / 8. Access word at address 48 Cache Miss Tag = 0, Set = 2, Offset = 0 Block 0 of Set Block 1 of Set Set Tag Contents Tag Contents 0 32, 33, 34, 35, 36, 37, 38, 39 1 0 8, 9, 10, 11, 12, 13, 14, 15 40, 41, 42, 43, 44, 45, 46, 47 2 16, 17, 18, 19, 20, 21, 22, 23 48, 49, 50, 51, 52, 53, 54, 55 3 24, 25, 26, 27, 28, 29, 30, 31 Seven accesses: words at addresses 48 through 51: Three cache hits. Total cache misses = 6. Total cache hits = 38. Hit Ratio = 38 / 44. Loop 2 44 total accesses. All are cache hits. Hit ratio = 82 / 88. Loop 3 44 total accesses. All are cache hits Hit ratio = 126 / 132 = 21 / 22 = 0.
- Suppose a computer using set associative cache has 2^21 words of main memory and a cache of 64 blocks, where each cache block contains 4 words. a) If this cache is 2–way set associative, what is the format of a memory address as seen by the cache, that is what are the sizes of the tag, set, and word fields? b) If this cache is 4–way set associative, what is the format of a memory address? ANSWER: If each cache block contains 4 words, then the memory is broken into blocks of 4 words each. The memory has 2^21 / 2^2 = 2(21 – 2)^ = 2^19 blocks. It has 21 address bits. a) If each block contains four words, the word offset address is 2 bits. There are 64 cache blocks, arranged into 32 sets, as each set has 2 blocks. The set address is 5 bits. The tag field is 21 – (2 + 5) = 14 bits. Bits 20 – 8 7 6 5 4 3 2 1 0 Field 14–bit tag Set Number Word b) If each block contains four words, the word offset address is 2 bits. There are 64 cache blocks, arranged into 16 sets, as each set has 4 blocks. The set address is 4 bits. The tag field is 21 – (2 + 4) = 15 bits. Bits 20 – 8 7 6 5 4 3 2 1 0 Field 15–bit tag Set Number Word
- (Paraphrased) A computer has an eight–bit memory address. It has a 16–byte cache with four bytes per block. The computer accesses memory words in this exact order: 6E, B9, 17, E0, 4E, 4F, 50, 91, A8, A9, AB, AD, 93, and 94. The format of the memory address is Bit 7 6 5 4 3 2 1 0 Field 4–bit tag Block Word Here is the cache configuration after the first four memory references. Block Tag Contents (represented by address) 0 E E0, E1, E2, E 1 1 14, 15, 16, 17 2 B B8, B9, BA, BB 3 6 6C, 6D, 6E, 6F
Access address 91 Block = 0 Tag = 9 Cache Miss Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 1 14, 15, 16, 17 2 B B8, B9, BA, BB 3 4 4C, 4D, 4E, 4F 3 cache misses 1 cache hit 4 total cache accesses. Access address A8 Block = 2 Tag = A Cache Miss Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 1 14, 15, 16, 17 2 A A8, A9, AA, AB 3 4 4C, 4D, 4E, 4F 4 cache misses 1 cache hit 5 total cache accesses. Access address A9 Block = 2 Tag = A Cache Hit Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 1 14, 15, 16, 17 2 A A8, A9, AA, AB 3 4 4C, 4D, 4E, 4F 4 cache misses 2 cache hits 6 total cache accesses. Access address AB Block = 2 Tag = A Cache Hit Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 1 14, 15, 16, 17 2 A A8, A9, AA, AB 3 4 4C, 4D, 4E, 4F 4 cache misses 3 cache hits 7 total cache accesses.
Access address AD Block = 3 Tag = A Cache Miss Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 1 14, 15, 16, 17 2 A A8, A9, AA, AB 3 A AC, AD, AE, AF 5 cache misses 3 cache hits 8 total cache accesses. Access address 93 Block = 0 Tag = 9 Cache Hit Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 1 14, 15, 16, 17 2 A A8, A9, AA, AB 3 A AC, AD, AE, AF 5 cache misses 4 cache hits 9 total cache accesses. Access address 94 Block = 1 Tag = 9 Cache Miss Block Tag Contents (represented by address) 0 9 90, 91, 92, 93 1 9 94, 95, 96, 97 2 A A8, A9, AA, AB 3 A AC, AD, AE, AF 6 cache misses 4 cache hits 10 total cache accesses. There are three options for the answer.
- If the first four memory references were cache hits, we then have 6 cache misses and 8 cache hits Hit Ratio = 8 / 14 = 0.5714 57.14%
- If the first four memory references were cache misses, we then have 10 cache misses and 4 cache hits Hit ratio = 4 / 14 = 0.2857 28.57%
- Answer based on the 10 memory access operations. Hit ratio = 4 / 10 = 0.40 40%
- Suppose a process page table contains the entries shown below. Using the format shown in Figure 6.15a, indicate where the process pages are located in memory. Index Frame Valid Bit 0 1 1 1 0 2 0 1 3 3 1 4 0 5 0 6 2 1 7 0 ANSWER: The process is using 8 pages, which we label as pages 0 through 7. In words, we have the following Virtual memory page 0 is in physical page frame 1 Virtual memory page 1 is not in memory Virtual memory page 2 is in physical page frame 0 Virtual memory page 3 is in physical page frame 3 Virtual memory page 4 is not in memory Virtual memory page 5 is not in memory Virtual memory page 6 is in physical page frame 2 Virtual memory page 7 is not in memory I prefer to use the format of Figure 6.11, which is simpler than figure 6.15a.
