Exam Two in ECE 2030 C Computer Engineering, Spring 2001, Exams of Computer Science

The exam questions for ece 2030 c computer engineering course held in spring 2001. The exam consists of 4 problems, each with multiple parts, totaling 6 pages. The problems cover various topics such as binary and decimal conversions, arithmetic operations, toggle cells, counter design, and building blocks. Students are required to perform calculations, design circuits, and identify errors.

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ECE 2030 C Computer Engineering Spring 2001
4 problems, 6 pages Exam Two 22 March 2001
2
Problem 1 (6 parts, 35 points) Numbers and Arithmetic
Part A (6 points) Convert these binary values (and powers of two) into decimal notation:
binary notation decimal notation
11001100.101 204.625
11100111 231
215 35 Thousand
Part B (6 points) Convert the following octal values into hexadecimal notation:
octal notation hexadecimal notation
236 010011110 = 9E
771177 111111001001111111 = 3F27F
52.25 101010.010101 = 2A.54
Part C (9 points) For each problem below, (a) compute the operations using the rules of addition, (b)
indicate whether an error occurs assuming all numbers are expressed using a four bit two’s
complement representation, and (c) indicate whether an error occurs assuming all numbers are
expressed using a four bit unsigned representation.
0 1 0 1
+ 1 0 1 11 1 0
+ 1 1 11 0 0 0
+ 1 0 1
addition
result 0 0 0 01 1 0 1 1 1 0 1
signed
error? no yes no
unsigned
error? yes no no
pf3
pf4
pf5

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4 problems, 6 pages Exam Two 22 March 2001

Problem 1 (6 parts, 35 points) Numbers and Arithmetic

Part A (6 points) Convert these binary values (and powers of two) into decimal notation:

binary notation decimal notation

11001100.101 204.

11100111 231

215 35 Thousand

Part B (6 points) Convert the following octal values into hexadecimal notation:

octal notation hexadecimal notation 236 010011110 = 9E

771177 111111001001111111 = 3F27F

52.25 101010.010101 = 2A.

Part C (9 points) For each problem below, (a) compute the operations using the rules of addition, (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.

addition result

signed error?

no yes no

unsigned error?

yes no no

4 problems, 6 pages Exam Two 22 March 2001

Part D (6 points) For each problem below, (a) compute the operations by negating and adding the lower number, (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.

  • 1 0 1 1
  • 1 1 0 0 subtraction result

signed error?

yes no

unsigned error?

yes yes

Part E (4 points) What is the minimum number of bits needed to represent the following decimal integers in an unsigned integer representation?

a) 45,387: 16 bits.

b) 32: 6 bits.

Part F (4 points) What is the minimum number of bits needed to represent the following decimal integers in a signed two’s complement integer representation?

a) 45,387: 17 bits.

b) -19: 6 bits.

4 problems, 6 pages Exam Two 22 March 2001

Problem 3 (3 parts, 20 points) Building Blocks

Consider a priority encoder with the following behavior:

In 2 In 1 In 0 O 1 O 0 Valid 0 0 0 X X 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 1 1

Part A (6 points) List the inputs (In 0 , In 1 , In 2 , and In 3 ) in increasing priority.

In 2 < In 0 < In 1 lowest priority 2 nd^ highest priority highest priority Part B (10 points) Design a 4-to-1 multiplexor using only pass gates and inverters. Clearly label all inputs and outputs. How many transistors are in your implementation? S 0

I 0

I 1

S 1

I 2

I 3

Out

Number of transistors: 16.

Part C (4 points) Design a 1-to-4 demultiplexor using the 4-to-1 mux you designed in part B (in icon form). Clearly label the inputs and outputs.

I 0

I 1

I 2

I 3

S 1

Out 4-to- MUX

S 0

In

O^0

O 1

O 2

O 3

S 0 S^1

4 problems, 6 pages Exam Two 22 March 2001

Problem 4 (1 part, 15 points) Registers and Timing

Consider the register implemented below.

In Out

En

Latch

In Out

En

Latch

mux

out

IN^ s

WE

OUT

A

phi1 phi

Assume the following signals are applied to your register. Draw the signal at point A (output of the first latch) and the output signal Out. Assume A and Out start at zero.

In

WE

Out

A