ECE 2030 Spring 2010 Computer Engineering Final Exam, Exams of Computer Science

The instructions and problems for the ece 2030 computer engineering final exam held in spring 2010. The exam consists of five problems, each with multiple parts, and covers various topics such as instruction set architecture, digital circuits, microcode, storage, and assembly language programming. Students are required to work the exam in pencil and show their work for maximum credit.

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2012/2013

Uploaded on 04/08/2013

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ECE 2030 1:00pm Computer Engineering Spring 2010
5 problems, 6 pages Final Exam 5 May 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have
a question, raise your hand and I will come to you. Please work the exam in pencil and do not
separate the pages of the exam. For maximum credit, show your work.
Good Luck!
Your Name (please print) ________________________________________________
1 2 3 4 5 total
30 32 26 24 23 135
1
pf3
pf4
pf5

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5 problems, 6 pages Final Exam 5 May 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name ( please print ) ________________________________________________ 1 2 3 4 5 total 30 32 26 24 23 135

5 problems, 6 pages Final Exam 5 May 2010 Problem 1 (3 parts, 30 points) Instruction Formats, Etc. Part A (9 points) Consider the instruction set architecture below with fields containing zeros. 000 0000 00 0000 00 0000 0 0000 0000 0000 opcode dest. reg. source 1 reg. immediate value What is the maximum number of opcodes? What is the number of registers? What is the range of the signed immediate value? Part B (9 points) Suppose the circuit below has the following input priority: I 1 > I 3 > I 0 > I 2. Complete the truth table by filling in the input values that would produce the given outputs and derive a simplified expression for O 1. I 3

I 2

I 1

I 0

O 1

O 0

I 3 I 2 I 1 I 0 V O 1 O 0

0 X X

O 1 =

Part C (12 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit unsigned and six bit two’s complement representations.

  • 111010
  • 11110 result unsigned error? signed error?

5 problems, 6 pages Final Exam 5 May 2010 Problem 3 (3 parts, 26 points) Microcode Using the supplied datapath, write microcode fragments to accomplish the following procedures. Express all values, except memory addresses, in hexadecimal notation. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field. In each part, modify only registers 7 & 8. Part A (5 points) R 7 =^ R 8 −^15 /^512 # X Y Z rwe im en im va au en s/ a lu en lf su en st ld en st en r/ w msel description 1 2 3 Part B (15 points) Compute mem[4000] ⊕ R 3 and store the result in mem[4004]. means bitwise logical XOR. # X Y Z rwe im en im va au en s/ a lu en lf su en st ld en st en r/ w msel description 1 2 3 4 5 6 Part C (6 points) R 7 =^18 ⋅ R 8 (multiply R 8 by 18) # X Y Z rwe im en im va au en s/ a lu en lf su en st ld en st en r/ w msel description 1 2 3 4

5 problems, 6 pages Final Exam 5 May 2010 Problem 4 (3 parts, 24 points) Storage Part A (12 points) Consider a 4 Gbit DRAM chip organized as 64 million addresses of 64 -bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two). total number of bits in address number of columns column decoder required ( n to m ) number of words per column type of mux required ( n to m ) number of address lines in column offset Part B (6 points) Implement a register below using only latches, pass gates, and inverters (all in icon form). Complete the behavior table at right. Recall that the CLK signal indicates a full Φ 1 Φ 2 cycle; so the output should be the value at the end of a cycle (for the given inputs). Out In

φ^1 φ^2

WE

Part C (6 points) Assume the following signals are applied to a register with write enable. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out is initially zero.

Φ^1

Φ^2

WE

In

Out

In WE Clk Out Out

A 0 ↑↓

A 1 ↑↓