ECE 2030 Midterm III: Electrical Engineering Questions, Exams of Computer Science

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ECE 2030

Section F

Midterm III

November 18

th

3:05 pm 4:25 pm

1. Draw the state diagrams for the following. Clearly label/define the meaning of each state and provide the state transition tables. a. Up-counter that is initialized to 4 and counts by 2 until 16 and is re- initialized to 4.

2. Show the implementation of a toggle cell using a flip flop and basic gates and logic building blocks. Use this toggle cell to design a counter to count from 0-

3. You have memory chips that provide 4M addresses and 4 bits at each address. Using these chips and any common building blocks you need, construct a memory system that will provide 8 M addresses and 8 bits at each address. a. How many address lines do you need? b. How many chips do you need? c. Draw a block diagram of the completed design. Clearly show all connections and signals including CE, RW the address lines and data lines.

d. Which chips are active on access to memory address 0x

b. Write the microcode to store the most significant byte of the word of location 0x1024, as the least significant byte of the word at location 0x1028. Assume little endian storage. (consistent use of either endian order will not penalized) .

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Description

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5. This question addresses components of the datapath a. Consider the logic unit that is part of the single cycle datapath and which has two inputs, A and B. We wish to complement the input A. What should be the value of lf?

b. Provide the result of the following operations on 16 bit two’s complements numbers i. Arithmetic right shift by 3 of 1111 0010 1100 1011

ii. Logical left shift by 4 of 1010 1010 1010 1111