EE143 Midterm #1 Solutions Sp 2003
Problem 1
(a) Either one of the following solutions will be acceptable.
Solution 1 (best) : One additional lithography mask is needed to protect the MOSFET region when
doing the poly-Si removal over ohmic contact area and p+ implant
Solution 2 (acceptable) :Two additional lithography masks are needed : 1) protect the MOSFET region
when doing the p+ implant for the ohmic contact regions (without poly-Si on top) , and 2) to protect the
ohmic contact region when doing the n+ implant for source/drain.
(b) All process steps same as MOSFET process. The key steps to add the p+ ohmic contact regions are
marked in italic
Starting wafer, p- Si
LOCOS process steps (Mask #1)
Gate oxide growth (thermal oxidation)
Undoped poly-Si deposition (CVD)
Pattern poly-Si (Mask#2)
Blanket As implant to form n+ poly-Si
and n+ source/drain regions
Pattern photoresist to cover all MOSFET regions
(Mask #3)-Extra mask
Etch away poly-Si over ohmic region
Boron implant to form p+ ohmic contact regions
Strip resist
Deposit CVD SiO2
Metal contact opening (Mask #4)
Al deposition
Al interconnect patterning (Mask #5)
p+
SiO2
p+
SiO2
p- substrate
p+
SiO2
p+
SiO2
p+
SiO2
p- substrate
p+
SiO2
p+
SiO2
p+
SiO2
p- substrate
n+ n+
p+
SiO2
p+
Gate
oxide
photoresist
High Dose Boron Ion Implantation
p+
SiO2
p+
SiO2
p- substrate
n+ n+
p+
SiO2
p+
Gate
oxide
photoresist
High Dose Boron Ion Implantation
p+
SiO2
CVD SiO2
p+
SiO2
Al
p- substrate
n+ n+
n+ poly Si
CVD SiO2
p+
SiO2
p+
CVD SiO2
CVD SiO2
MOSFET
Ohmic Contact
to substrate
Gate
oxide
p+
SiO2
CVD SiO2
p+
SiO2
Al
p- substrate
n+ n+
n+ poly Si
CVD SiO2
p+
SiO2
p+
CVD SiO2
CVD SiO2
MOSFET
Ohmic Contact
to substrate
Gate
oxide
p+
SiO2
p+
SiO2
p- substrate
poly Si
p+
SiO2
Gate
oxide
p+
SiO2
p+
SiO2
p- substrate
poly Si
p+
SiO2
Gate
oxide
p+
SiO2
p+
SiO2
p- substrate
poly Si
p+
SiO2
Gate
oxide
p+
SiO2
p+
SiO2
p- substrate
n+ n+
n+ poly Si
p+
SiO2
Gate
oxide
Arsenic Ion Implantation
p+
SiO2
p+
SiO2
p- substrate
n+ n+
n+ poly Si
p+
SiO2
Gate
oxide
Arsenic Ion Implantation
