Testing - Microcontroller Systems - Lecture Slides, Slides of Microcontrollers

In the class of computer sciences, we have a special class for the Microcontroller Systems. The main points in these slides are:Testing, Embedded Systems, Chip Testing, Built-In Self Test Blocks, Bed of Nails Technique, Joint Test Access Group, Boundary Scan Register, Internal Logic, Pins Control Operation, Software Testing, Port Operation

Typology: Slides

2012/2013

Uploaded on 04/24/2013

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Testing
Just like in software, embedded systems need to be
tested and debugged
However, in these systems, testing includes multiple facets!
Chip/component verification
Circuit boards / External devices
Software, including system startup and configuration
Hardware has a much higher penalty for correctness mistakes
You can’t “patch” hardware
Recalls are expensive (on several levels)
Q: How many Pentium designers does it take to screw in a light bulb?
A: 1.99904274017, but that's close enough for non-technical people.
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Testing

  • Just like in software, embedded systems need to be

tested and debugged

  • However, in these systems, testing includes multiple facets!
    • Chip/component verification
    • Circuit boards / External devices
    • Software, including system startup and configuration
  • Hardware has a much higher penalty for correctness mistakes
    • You can’t “patch” hardware
    • Recalls are expensive (on several levels) Q: How many Pentium designers does it take to screw in a light bulb? A: 1.99904274017, but that's close enough for non-technical people.

Chip Testing

  • Post-production testing of a chip (in a basic test harness) became a

very difficult (and expensive) part of a chip’s production

  • Involves the design of large test suites to send through the pins
  • Involves very expensive test harnesses to be able to run these quickly
  • Modern systems often use B uilt- I n S elf T est (BIST) blocks within the

chip that will run a number of internal tests automatically

  • Example: RAM test in your PC BIOS

JTAG

  • Mid/Late 80s: a group of companies banded together to define

standards for including hardware to do this testing

  • Joint Test Access Group (JTAG)
  • 1990: IEEE made it standard 1149.
  • IEEE Standard Test Access Port and Boundary Scan Architecture
  • Boundary Scan
  • Chip can be put into a “test mode”, where built-in testing blocks take over the use of the pins

JTAG

  • The TAP controller runs the

show for the internal logic.

  • 4 pins control operation:
    • 2 Serial Data pins
      • TDI (Test Data In)
      • TDO (Test Data Out)
    • TCK (Test Clock)
    • TMS (Test Mode Select)
  • Required Instructions:
    • EXTEST
    • SAMPLE/PRELOAD
    • BYPASS
  • All individual cells together form

the “Boundary Scan Register”

  • MPC555: 346 bits

Background Debug Mode (BDM)

  • Most embedded processor manufacturers now include a “Development

Port” of some kind to support remote debugging

  • Observe contents of registers and memories
  • Hardware breakpoints
  • Single-step
  • Ref: MPC555 Manual, Section 21

Development Port Operation

  • 3 pins:
    • DSCK
    • DSDI
    • DSDO
  • When “debug mode” is

entered, the processor stops

fetching instructions from

memory

  • Instructions are entered

through the DPIR (instruction

register)