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An in-depth exploration of various concepts in computer architecture, including datapath implementation, pipelining, instruction level parallelism, and memory hierarchy system. It covers topics such as single/multiple cycle approaches, pipeline hazards, dynamic scheduling, tomasulo's approach, and static scheduling. Students will gain a solid understanding of these fundamental concepts and their role in enhancing processor performance.
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It consists of registers, internal buses, arithmetic units and shifters Each register in the register file has:
In the Single Cycle implementation, the cycle time is set to accommodate the longest instruction, the Load instruction. In the Multiple Cycles implementation, the cycle time is set to accomplish longest step, the memory read/write Consequently, the cycle time for the Single Cycle implementation can be five times longer than the multiple cycle implementation.
Data Hazards occur when attempt is made to read invalid data Data hazard can be removed by using stall and forwarding techniques Control hazards occur when an attempt is made to branch prior to the evaluation of the condition Four ways to handle control hazards
Module 4: Instruction Level parallelism Simple pipeline facilitates in-order execution Whereas, in order to enhance the performance of the pipeline, we want to begin execution as soon as the data operands are available, i.e., out-of-order execution Out-of-order execution may introduce data hazards of type WAR and WAW Instruction Level Parallelism can be achieved by Hardware or Software
Module 4: Instruction Level Parallelism In SW parallelism, the dependencies are defined by program result in hazards if HW cannot resolve HW exploiting ILP works when dependence cannot be determined at run time These hardware techniques to exploit ILP are referred to as Dynamic Scheduling techniques
Module 4: Instruction Level Parallelism Tomasulo's Approach for IBM 360/91 to achieve high Performance without special compilers Here, the control and buffers are distributed with Function Units (FU) Registers in instructions are replaced by values or pointers to reservation stations(RS) ; i.e., the registers are renamed Unlike Scoreboard, Tomasulo can have multiple loads outstanding
Module 4: Instruction Level Parallelism
Module 4: Instruction Level Parallelism The major hardware-based techniques studied are summarized here: Technique Hazards type stalls Reduced
Module 5: Static Approach for ILP
Module 5: Static Approach for ILP
Module 6: Memory Hierarchy System Here, we discussed how the gap between the speed of processor and the storage devices - DRAM, SRAM and Disk is increasing with time We studied that in order to obtain high speed storage at the cheapest cost per byte, different types of memory modules are organize in hierarchy, based on the:
Module 6: Memory Hierarchy System The principle of locality states that to obtain data or instructions of a program, the processor access, at any instant of time, a relatively small portion of the address space of the fastest memory closet to the processor There are two different types of locality: Temporal locality is the locality in time Spatial locality is the locality in space
