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Verification Project - HDL Design - Lecture Slides, Slides of Verilog and VHDL

During the course work of the HDL design, the key points in the lecture slides are:Verification Project, Bit Adder, Generator, Counters Configured, Fault Simulation, Resolved, Package, Simulation Type, General, Architecture

Typology: Slides

2012/2013

Uploaded on 05/07/2013

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Lect 35 – Verification Project 2
•Design of fault tolerant circuit testing and fault
simulation.
•What needs verified
–A SEC/DED 8-bit adder with a SED counter stimulus input
generator (need figure)
–Provided with 8-bit SEC/DED adder
–Provided with 8 bit counters configured with adder in a
fill8 logic unit.
–Provided with package for fbit. – fault simulation bit type
–Provided with package for fsim_logic – resolved fault
simulation type
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Lect 35 – Verification Project 2

• Design of fault tolerant circuit testing and fault

simulation.

• What needs verified

– A SEC/DED 8-bit adder with a SED counter stimulus input

generator (need figure)

– Provided with 8-bit SEC/DED adder

– Provided with 8 bit counters configured with adder in a

fill8 logic unit.

– Provided with package for fbit. – fault simulation bit type

– Provided with package for fsim_logic – resolved fault

simulation type

The SEC/DED adder

• In general the

architecture is

Half

Add

a(0) b(0) a(1) b(1)

ttcout(0)

ttsum(0)

Full

Add

ttcout(1)

ttsum(1)

Half

Add

abar(0) bbar(0) abar(1) bbar(1)

tdcout(0)

tdsum(0)

Full

Add

tdcout(1)

tdsum(1)

Half

Add

a(0) b(0) a(1) b(1)

btcout(0)

btsum(0)

Full

Add

dbcout(1)

btsum(1)

Half

Add

abar(0) bbar(0) abar(1) bbar(1)

bdcout(0)

bdsum(0)

Full

Add

bdcout(1)

bdsum(1)

Mux

sum

ttsum btsum

tserr

Mux

cout

ttcout btcout

tcerr

ttsum(0) tdsum(0)

ttsum(1) tdsum(1)

tserr

tcerr

ttcout(0) tdcout(0)

ttcout(1) tdcout(1)

bcerr

btcout(0) bdcout(0)

btcout(1) bdcout(1)

btsum(0) bdsum(0)

btsum(1) bdsum(1)

bserr

tserr bserr

tcerr

bcerr

corerr

tserr bserr

tcerr

bcerr

ttsum(0)

ttsum(1)

btsum(0)

btsum(1)

Overhead of fault simulation

• What is overhead????

• On every gate evaluation a random number is

generated. SO LOTS OF OVERHEAD

computation.

• Part of work is to evaluate that overhead.

– How to do it? Run the adder (type bit exhaustive)

and have the time. Run the adder (type fbit) and

have the time. Run the adder (type fsim_logic)

and have the time. Include this in the report.

What may need to be added

• Fbit_logic package needs to include a type

conversion function to convert to/from type

bit. This is such that the testbench can

generate the test transactions without error.