Overview - HDL Design - Lecture Slides, Slides of Verilog and VHDL

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Introduction to VHDL

Lecture overview

• An introduction to VHLD

• At the structural level

• At the mixed level

• At the behavioral level

Common to all systems

• Have source HDL file

• Structure of generated files is common

Source Files VHDL Library Files Analysis (Compile) Simulation (^) Synthesis

A First Example

• Desire to do a VHDL description of a full adder.

• A device consists of

– An Interface

– An operational part

• Interface – The INPUTS AND OUTPUTS

• Operational Part – The FUNCTIONAL BEHAVIOR

Signals/Port Modes/Types

• PORT(a,b,cin:IN bit; sum:OUT bit; cout: OUT bit);

• Signals : Names referenced in the Port Clause are

signals.

– A,b,cin,sum,cout represent wires of the physical unit.

– SIGNALS are objects that have both a value and a time

component.

• Port Modes : In this example you have inputs and

outputs. The Port Mode specifies the direction of

the signal transfer and a couple of other

properties of the port.

Signals/Port Modes/Types

• Modes :

– IN – signal can only be used (i.e., can only be read or can

only be used on the right-hand-side of an equation).

CANNOT BE ASSIGNED TO!!

– OUT – signal value can only be written. Cannot be seen or

used in the design as it is an output and therefore external.

– INOUT – signal can be both written to (assigned to) and

read (used). However, signals of thie type are connected

to busses and therefore this signal mode requires the

signal to be resolved.

– BUFFER – signal value can be written to and used internally

in the design.

Architectural Design Unit

• Specifies the operational part

– ARCHITECTURE identifier OF entity_id IS

– [declarations]

– BEGIN

– [architecture_statement_part]

– END [identifier];

– [architecture_statement_part] – Any concurrent

statement of the language

Example of Architecture

• For a full adder

– ARCHITECTURE one OF fulladder IS

– BEGIN

– sum <= a XOR b XOR cin;

– cout <= (a AND b) OR (a AND cin) OR (b

– AND cin);

– END one;

A Multibit Adder Example

• Will model using a dataflow style

– Bit Vectors for ports and individual signals internally

– Bit Vectors for ports and bit vectors internally

• The Entity Design Unit (same for both)

– ENTITY mb_adder IS

– PORT(a,b : IN bit_vector(3 downto 0);

– cin : IN bit; cout : OUT bit;

– sum : OUT bit_vector(3 downto 0));

– END mb_adder;

The first dataflow Architecture

• ARCHITECTURE one OF mb_adder IS
• SIGNAL c : BIT_VECTOR (4 downto 0);
• BEGIN
• c(0) <= cin;
• sum(0) <= a(0) XOR b(0) XOR c(0);
• sum(1) <= a(1) XOR b(1) XOR c(1);
• sum(2) <= a(2) XOR b(2) XOR c(2);
• sum(3) <= a(3) XOR b(3) XOR c(3);
• c(1) <= (a(0) AND b(0)) OR (a(0) AND c(0)) OR
• (b(0) AND c(0));
• c(2) <= (a(1) AND b(1)) OR (a(1) AND c(1)) OR
• (b(1) AND c(1));
• c(3) <= (a(2) AND b(2)) OR (a(2) AND c(2)) OR
• (b(2) AND c(2));
• c(4) <= (a(3) AND b(3)) OR (a(3) AND c(3)) OR
• (b(3) AND c(3));
• Cout <= c(4);
• END one;

Operations on Type BIT

• Consider the following declaration

• SIGNAL x,y : bit;

• Logical Operations

• x AND y Also have shift operations
• x OR y arithmetic shifts ASR ASL
• x NAND y
• x NOR y logical shifts LSR LSL
• x XOR y
• x XNOR y these work on vectors
• NOT y

• NOTE: For logical expressions the equation is only

evaluated until the result is determined.

Assignment and Relational Operators

• Assignment Operators
  • For signal <=
  • For variables :=
• Relational Operators
  • (x=y) (x/=y) (x<=y) (x>=y)
  • Example of use
  • (x=‘1’) AND (y=‘0’)

Structural Example for a full adder

• The first part
  • ARCHITECTURE structural OF full_adder IS
  • -- Must declare the components that are to be used
  • COMPONENT and
  • PORT (A,B : IN BIT; Z : OUT BIT);
  • END COMPONENT ;
  • COMPONENT xor
  • PORT (A,B : IN BIT; Z : OUT BIT);
  • END COMPONENT ;
  • COMPONENT or
  • PORT (A,B,C : IN BIT; Z : OUT BIT);
  • END COMPONENT ;
  • -- State which library to find them in and which architecture to use.
  • FOR ALL : and2 USE ENTITY WORK.and2(behavioral);
  • FOR ALL : xor2 USE ENTITY WORK.xor2(behavioral);
  • FOR ALL : or3 USE ENTITY WORK.or3(behavioral);
  • -- Declare local signals required.
  • SIGNAL addt. ct1, ct2, ct3 : BIT;

The second part of the

Architecture

• From the BEGIN

• BEGIN
• G1: xor2 PORT MAP(a,b,addt);
• G2: xor2 PORT MAP(addt, cin, sum);

• G3: and2 PORT MAP(a,b,ct1);
• G4: and2 PORT MAP(a,cin,ct2);
• G5: and2 PORT MAP(b,cin,ct3);

• G6: or3 PORT MAP(ct1,ct2,ct3,cout);

• END Structural;